VSORA's new coprocessor claims to be able to achieve the computing power required for full L5 autonomous driving

Even though the engineering community is investing billions of dollars and thousands of hours into making cars autonomous, there’s still a long way to go.

Today's best commercial products reach Level 2 (L2) on the SAE driving automation scale of 5. In summary, to reach Level 5 (L5), both hardware and software need to improve.

SAE levels of driving automation. Image courtesy of Autopilot Review

VSORA is a startup company dedicated to developing chips and IP to advance the autonomous driving revolution in automobiles.

Last week, VSORA announced a new family of processors that support petaFLOPS.

This article will explore the high-level hardware required to achieve Level 5 autonomy and take a deep dive into VSORA's latest chipset family.

The need for advanced hardware

Some believe that one of the biggest barriers to achieving Level 5 autonomous driving is the poor performance of our current hardware. Basically, multiple aspects of self-driving cars require extremely high computing power.

First, all self-driving cars need to process a lot of data. Today, vehicles typically use up to 40 sensors on the system (e.g., cameras, lidar), many of which generate extremely high throughput.

To use all this data effectively, vehicles require extremely high computing power.

The flow of data in an autonomous vehicle. Image courtesy of Abalta

This challenge is further exacerbated by the real-time requirements of autonomous vehicles. These vehicles require real-time decision making, which means that within milliseconds, data must be collected, fused, and processed, and then an execution decision needs to be made.

To achieve this across massive amounts of data requires enormous computing power.

VSORA’s latest chipset promises to advance and ease this computing challenge.

VSORA's Tyr chipset

Last week, startup VSORA released a new chip family that it claims will help support up to L5 autonomous driving.

The Tyr series chips are companion processors designed to offload heavy AI and signal processing tasks from a system's main processor.

This capability is demonstrated by how the family is built around the VSORA multicore architecture used in its AD1028, which won “Best Processor IP” in 2020.

Overview of the AD1028 architecture used in the Tyr series. Image courtesy of VSORA

The architecture combines an advanced digital signal processing (DSP) unit for complex signal processing, an AI unit consisting of a series of identical cores, and tightly coupled memories.

The flagship of the series is the Tyr3, which features 256k MACs in its AI core and 2,048 ALUs for DSP applications.

Tyr3 is said to be able to achieve 1,032 TFLOPS of computing power while consuming only 10 watts of power.

According to VSORA, this new chip can significantly simplify the leap from L2 to L5 by providing a high-performance, easy-to-integrate solution for existing hardware infrastructure.

The push toward Level 5 autonomous driving

While some, like VSORA, claim that our current hardware is not ready to reach L5, others disagree.

Notably, Musk was quoted as saying that he believes the hardware within Tesla is sufficient to support Level 5 autonomous driving: The real hurdle for them seems to be the software.

Regardless of who's right, there's no doubt that improvements in hardware can only be a good thing. VSORA appears to have done just that with its new Tyr series of companion processors.