Abstract
Use FSM to implement the car taillight control circuit on DE2 .
Introduction
Use environment: Quartus II 9.1 web edi TI on + DE2
Assume that there are three indicator lights on each side of the rear of the car , and you are required to design a circuit to achieve the following functions:
1. When the car is driving normally, all six lights on both sides of the rear are off;
2. When braking, the lights on both sides of the tail will light up, indicating an emergency state;
3. When turning right, the three lights on the right will light up in a rightward order, with only one light on at a time, and all lights on the left will go out;
4. When turning left, the three lights on the left will light up in a circular manner in a leftward direction, with only one light on at a time, and all lights on the right will go out;
5. When braking for a right turn, the three lights on the right will light up in sequence, and all the lights on the left will light up; when braking for a left turn, the three lights on the left will light up in sequence, and all the lights on the right will light up;
6. When reversing, the six lights on both sides of the rear will flash continuously at a certain frequency.
Assume that the input clock signal of the circuit is cp, and the frequency of cp is equal to the flashing frequency required by the taillights of the car .
State diag ram
1. Output status table
2. State diagram as shown in Figure 1 Car taillight state diagram
Figure 1 Car taillight status diagram
After completing the state diagram, a large part of the system design is completed. The remaining work is to use HDL to describe the circuit, simulate, download, and verify the functions.
Complete code
/*
(C) yf.x 2010 http://halflife.cnblogs.com/
Filename: part1.v
Compiler : Quartus II 9.1 Web Edition
Descrip TI on: Demo how to use Switch and led
Release : 03/23/2010 1.0
*/
t ai llight.v
Specify
Conclusion
The most creative and difficult part of the whole design is to design the state diagram. In the state transition description part, I used one-hot code and included the output state in the last 6 bits of the state code. The advantage of this is that it simplifies the decoding circuit and avoids glitches . Because it is designed for the FPGA on DE2 , it occupies more trigger resources than other encoding methods. But the advantage of FPGA is that it has more trigger resources. J
At present, the known problems in the verification are that the taillight of the car is a classic course design. It is described in detail in Chapter 7 of John.F wakerly's "Digital Design - Principles and Practice", but it does not include the 5th item (braking when turning). Therefore, I am still not sure that the design state diagram is perfect enough. When verifying on DE2, when turning, the brake must turn first (activate the turning signal) and then brake to display the state of the above output state table normally. Of course, this is also determined by the highest priority of braking. No major problems have been found, but I always feel that it is not perfect. I hope that interested enthusiasts can test it and see how to improve it.
Reference
1. John F. Wakerly, Principles and Practice of Digital Design (4th) Machinist
2. Roger, " Verilog HDL and Digital ASIC Design Basics" Huake
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