Design of digital timing control circuit based on CPLD technology

As a new type of tracking and positioning device, the six-degree-of-freedom electromagnetic sensitive positioning system can determine the six parameters of the target in real time. It has been widely used in airborne fire control systems (helmet sights), precision medical equipment, and single-soldier combat simulation training [1, 2]. The tracking system consists of two parts: hardware consisting of a sinusoidal signal transmitting circuit and a sensitive signal receiving circuit, and an algorithm program for solving target parameters from sensitive received data. The positioning calculation accuracy is subject to the errors of the above two parts. At present, without considering the influence of environmental factors, the algorithm error has reached a level of less than 1 milliarc. Therefore, the error of the hardware circuit has become the main factor restricting the positioning accuracy of the system. According to the working principle, the system excites the transmitting antenna in sequence, and then calculates the target parameters according to the receiving matrix composed of the sensitive antenna receiving signal. However, as an analog device of the timing control circuit, there are unavoidable temperature drift and time drift problems, which greatly affects the accuracy of the timing transmission and reduces the accuracy of the system positioning calculation. In order to solve this problem, this paper uses CPLD digital control technology to improve the timing circuit. CPLD (Complex Programmable Logic Device) is a new generation of digital logic devices, which has the characteristics of fast speed, high integration, strong reliability, and users can repeatedly program or dynamically reconstruct its logic functions. The timing circuit designed using CPLD chips and digital control technology can improve the accuracy of timing control to nanoseconds, and it works stably and is not affected by temperature, which is conducive to improving the positioning accuracy of the system.

System Principle

The working principle of the six-degree-of-freedom electromagnetic sensing system [2] is as follows: the three axes (x, y, z) of the transmitting antenna are used as the reference coordinate system. The position parameters of the receiving antenna relative to the transmitting antenna are represented by the distance, azimuth and elevation angle, and the attitude parameters are represented by the yaw angle, pitch angle and roll angle. These six parameters are the target parameters to be calculated, namely the six degrees of freedom, see Figure 1. The system consists of a sinusoidal signal generator, a timing control circuit, a power amplifier circuit, a three-axis ring antenna, a receiving signal amplifier circuit, a detection phase judgment circuit, and a data acquisition and parameter calculation circuit, see Figure 2.

When the system is working, the transmitting circuit excites the three loop antennas of the transmitting antenna in turn in a time-division excitation manner. Each time the excitation is performed, the receiving antenna (three in total) receives three signals. In one excitation cycle, the receiving antenna receives a total of nine signals. The receiving matrix composed of these nine signals can be used to calculate all target parameters.

Timing control circuit design

From the working principle of the system, it can be known that the transmission signal needs to stimulate the three transmitting antennas in turn in a time-division manner. Therefore, the accuracy of timing control is very important in improving the accuracy of the system tracking and positioning calculation. However, due to the limited accuracy of analog components such as capacitors used in the original timing circuit and the influence of temperature on analog components, the timing control signal will drift and the accuracy is low, which causes a large deviation between the actual value of the receiving matrix element and the theoretical value, affecting the calculation accuracy of the system. In order to improve the accuracy of the system positioning calculation, the accuracy of the system timing control must be improved. Based on this, this paper designs a new type of digital timing control circuit on the MAX II series chip EPM570T100C5 based on CPLD digital control technology, which greatly improves the accuracy of the system timing control, thereby improving the calculation accuracy of the system. The circuit composition is shown in Figure 4.

The precise clock signal is provided by a 32MHz high-precision crystal oscillator. The MAX II chip EPM570T100C5 generates precise timing control signals. EPM570 is a world-class low-cost device suitable for implementing any digital control function. The chip adopts a non-volatile single-chip solution to solve board-level problems such as insufficient processor I/O pins, manage power-on sequencing, configure other more complex devices, or implement the conversion of incompatible interfaces ("glue logic") at low cost. It has the advantages of low cost, zero power consumption, small package, instant start, non-volatility, and in-system programmability (ISP). CD4053 completes the time-division excitation of the sinusoidal signal according to the precise timing digital control signal provided by the CPLD chip.

Software Design

During the CPLD development process, the CPLD development software Quartus II provided by Altera was used, which supports most of Altera's devices. In order to shorten the design cycle and reduce the design complexity, Quartus II includes workgroup calculation, integrated logic analysis function, EDA tool integration, multi-project support, enhanced recompilation and IP integration. The design process adopts a top-to-bottom design concept, with the top layer based on functional block design and the bottom layer's specific functions implemented through VHDL language programming.

Top-level design

The top-down design process starts with system-level functional design in the software, and then designs and verifies different functional blocks in the system separately. The advantage of this design method is that new functional modules can be continuously added to the design to improve the system's functions.

Three functional modules are designed in the top layer: pre-scaling module, sub-scaling module, and decoding module. The functional block diagram is shown in Figure 5. When the system is powered on, the crystal oscillator first provides the system with an accurate baseband signal. The pre-scaling module converts the original baseband signal into a 400Hz timing signal. The 400Hz signal is divided into two and four by the sub-scaling module [6,7]. The 100Hz and 200Hz signals obtained by the frequency division are input into the decoder module [7]. The decoding generates an accurate timing control signal with a timing interval of 2.5ms.

Bottom-level design

After the system function verification is completed, the abstract top-level design is refined to the low-level design. The bottom-level software design is designed based on the three major functional modules in the top-level software. The module design is completed using VHDL language description. After compilation, synthesis, and simulation, the bottom-level design file is generated for the top-level design to call. Taking the fenpin module as an example, some of the programs are as follows:

architecture rt of fenpin is

signal temp :std_logic_vector(1 downto 0);

begin

process(clk,temp,en)

begin

if en='1' then

if rising_edge(clk) then

temp<=temp+'1';

end if;

null;

end if;

end process;

clk2<=temp(0);

clk4<=temp(1);

end rt;

System Simulation and Verification

After the software design is completed, the chip is specified as EPM570T100C5 through Quartus II software, and the pins are assigned according to the circuit schematic, the pin functions of the CPLD are set, and then the compiler is started to compile the project. The compiler will perform error checking, netlist extraction, logic synthesis and device adaptation, and then perform behavioral simulation, functional simulation and timing simulation, and finally use the download cable to download the file to the chip through JTAG programming to generate the hardware circuit.

FIG6 is the result of the system software simulation. It can be seen from the figure that the generated timing control signal is stable and has an accuracy of nanoseconds.

Figure 7 shows the actual working state of the system observed by the logic analyzer when the program is downloaded to the target chip and the hardware is working. It can be found that the actual working state of the system is consistent with the theoretical design concept. The three-way timing control signal in the figure has high accuracy and stable state, without burrs and drift, which lays the foundation for improving the stability of the system and the accuracy of the receiving matrix.