Design of protocol converter based on DSP+ARM architecture

When testing flight control components, the telemetry receiving device is far away from the information processing center, and the amount of data to be tested is extremely large. If the traditional dedicated line is used to transmit telemetry data, the transmission time will take several hours, which cannot meet the requirements of fast processing. Therefore, it is necessary to develop a protocol converter to complete the lossless, real-time, and long-distance communication between the tested data and the remote host computer, and to receive the control instructions of the host computer to realize remote interaction of the working status, and the test personnel can complete all tests through the human-machine interface of the host computer.

1. System composition and working principle

Considering the requirements of system real-time and reliability, the Ethernet port is selected as the data forwarding interface between the protocol converter and the remote host computer, and the high-speed serial port is used as the communication mode of the control port, and the DSP+ARM architecture hardware solution is adopted. The system block diagram is shown in Figure 1. Basic working principle: FPGA is used as a data preprocessor to complete data preprocessing tasks such as conversion of parallel data to serial data; DSP reads the data processed by FPGA and completes data compression; ARM is used as a central processing controller, which mainly reads the encoded data from the DSP system and completes the task of real-time communication with the host computer through Ethernet. The host computer demodulates various physical variables according to the data transmission protocol and the product data telemetry protocol, records and stores them.

Figure 1 Protocol converter system block diagram

The tester completes the tasks of remote setting of working status and querying information interaction through the host computer.

2. Hardware Design

2.1 TMS32OC6416 and its peripheral circuit design

The DSP chip used is TMS320C6416 from TI. This is a high-speed fixed-point DSP launched by TI. It has a powerful CPU, up to 1 MB of RAM and rich peripheral interfaces. The peripherals include flexible external memory interfaces EMIFA and EMIFB that provide seamless interfaces for CPU to access peripheral devices, a PCI interface that makes it easy for DSP to seamlessly connect to an external main CPU with PCI function through the PCI interface, a 16/32 bit wide asynchronous parallel interface HPI (sharing the same pins as Pal), an enhanced EDMA that provides 64 bit data channel access, etc. TMS320C6416 is powered by 3.3 V and 1.4 V power supplies, of which I/O is powered by 3.3 V power supply and the core is powered by 1.4 V power supply. TMS320C6416 has a JTAG standard test interface and corresponding controller that complies with the IEEE1149.1 standard, so that the DSP system can be connected to a PC through an emulator for online debugging.

2.1.1 Interface circuit between DSP and SDRAM and Flash

The DSP processor TMS320C6416 has two EMIF bus interfaces, namely EMIFA with a width of 64 bits and EMIFB with a width of 16 bits. The EMIFA interface has the functions of interfacing with 8, 16, 32, and 64 bit systems, and the EMIFB interface port supports 8 bit and 16 bit systems. EMIFA is divided into four storage spaces, ACE0 to ACE3, each of which can be independently configured to seamlessly connect multiple types of memory (such as SRAM, Flash RAM, DDR RAM).

In order to improve the system running speed, two SDRAM chips are expanded as the program running space, data and stack area. The SDRAM chip uses synchronous memory MT48LC2M32B2TG, whose capacity is 2M×32 bits. TMS-320C6416 realizes seamless connection with two SDRAM chips through EMIFA interface.

TMS320C6416 has no internal Flash memory. In order to form an independent system, an external extended Flash memory AM29LV400B is used to store programs. When the system is reset, the program is loaded from the Flash. TMS320C6416 realizes seamless connection with the Flash chip through the EMIFB interface.

2.1.2 Interface circuit between DSP and FPGA

Since the sampling speed and storage space of the DSP processor TMS320C6416 are limited by its own constraints, tasks such as data collection, flow control and data preprocessing are completed by FPGA. The FPGA chip uses the XC3S500E in the Spartan-3E series of Xilinx's low-cost field programmable gate array. The XC3S500E chip integrates ⒛ Block RAMs, and the 18 Kbit module memory in each RAM block is a fully synchronous, true dual-end memory. Users can read from or write to each port independently (but the same address cannot be read and written at the same time). In addition, each port has an independent clock, and the data width of each port can be configured independently. [page]

In this protocol converter, DSP is connected to FPGA through EMIFA interface, realizing seamless connection between DSP and FPGA Block RAM, so that the communication problem between DSP and FPGA is converted into DSP access to its EMIFA peripherals, achieving the purpose of improving the real-time performance of the system. In order to maintain synchronization between FPGA and DSP, the clock of FPGA is directly provided by the phase-locked loop inside DSP. The interface diagram of DSP processor TMS320C6416 and FPGA is shown in Figure 2.

Figure 2 Schematic diagram of TMS320C64l6 and FPGA interface

2.2 S3C451OB and its peripheral circuit design

The ARM chip used is Samsung's S3C4510B. S3C4510B is a cost-effective 16/32 bit RISC microcontroller based on Ethernet applications, which contains a 16/32 bit ARMTTDMI RISC processor core designed by ARM. S3C4510B provides a relatively complete set of general peripherals, thus minimizing the consumption of the entire system. Because it has many commonly used functional modules, it also eliminates the trouble of adding and configuring additional devices. The functions integrated on the chip mainly include the following aspects: 3.3 V ARM core and 3.3 V external I/O, a microprocessor with a clock frequency of 50 MHz; 8 KB Cache/SRAM; a 10/100 Mb/s Ethernet controller, MII interface; 2 HDLC channels, each channel can support 10 Mb/s; 2 UART channels, 2 DMA channels, 2 32-bit timers/counters; 1 channel IIC interface, 18 programmable I/O ports; interrupt controller, supporting 21 interrupt sources, including 4 external interrupts; supporting SDRAM, SRAM, Flash, etc.; with extended external bus and JTAG interface, supporting software development and hardware debugging.

This design uses the ARM microcontroller S3C4510B because it has an integrated Ethernet controller and strong peripheral expansion capabilities. The S3C4510B and its peripheral chips Flash and SDRAM form the core of the entire system, responsible for controlling and coordinating the work of each module, and realizing Ethernet communication with the remote host computer. This design expands the internal SDRAM and ROM of the S3C4510B. Two SDRAM chips HY57V641620 are connected in parallel to build a 32-bit SDRAM storage system; a Flash chip HY29LV160 is used to build a 16-bit Flash memory system.

2.2.1 Interface circuit between ARM and DSP

Since the ARM microcontroller needs to realize the coordinated control and network functions of the entire system, and the DSP processor needs to perform complex calculations, it is necessary to realize data exchange between the ARM and DSP. To some extent, the speed of data exchange between the ARM and DSP determines the operating speed and performance of the entire system.

The DSP processor TMS320C6416 integrates a 16/32 bit wide host interface HPI. HPI selects HPI16 or HPI32 through the bootstrap at reset and the device configuration pin HD5. UPI has two address lines HCNTRL［1:0］, which are responsible for addressing the internal registers of HPI. HPI has only three 32 bit internal registers, namely the control register HPIC, the address register HPIA and the data register HPID. Only by performing corresponding read and write operations on the above three registers, the DSP memory space can be accessed.

Since there is no external interface in the ARM microcontroller S3C4510B that fully complies with the HPI interface timing of the DSP processor TMS320C6416 that can be used directly, the external I/0 interface in the S3C4510B with the timing closest to the HPI interface timing is selected to connect to the TMS320C6416. The interface diagram of TMS320C6416 and S3C4510B is shown in Figure 3. As shown in Figure 3, TMS320C6416 and S3C4510B are connected through separate 32-bit data lines HD0~HD31 and 8 control lines. S3C4510B accesses the RAM inside the DSP and some other external resources through HPI. In the entire process of communication and data exchange between ARM and DSP through HPI, except for interrupting ARM and clearing the interrupt sent by ARM, which requires the participation of DSP itself, DSP is in a passive position in other operations. So for ARM, DSP is equivalent to an external SDRAM. [page]

Figure 3 Schematic diagram of the interface between TMS320C6416 and S3C4510B

2.2.2 Ethernet interface circuit

The ARM microcontroller S3C4510B has an embedded Ethernet controller that supports Media Independent Interface (MII) and Buffered DMA Interface. It can provide 10/100 Mb/s Ethernet access in half-duplex or full-duplex mode. In half-duplex mode, the controller supports CSMA/CD protocol, and in full-duplex mode, it supports IEEE802.3 MAC control layer protocol. Therefore, S3C4510B actually contains Ethernet MAC control, but does not provide a physical layer interface, so RTL8201 is used as the physical layer interface of Ethernet. The signal sending and receiving ends TPRX+, TPBX-, TPTX+, and TPTX should be connected to the transmission media through the network isolation transformer and RJ45 interface. The schematic diagram of the Ethernet interface is shown in Figure 4.

Figure 4 Schematic diagram of Ethernet interface

3. System software design

Since the ARM microcontroller S3C4510B is needed to realize the coordinated control and network functions of the entire system, the embedded operating system uClinux is transplanted on the S3C4510B. uCLinux is an operating system with a complete TCP/IP protocol. The real-time RT-Linux module is added to uCLinux to meet the real-time requirements of the embedded operating system, and the uCLinux system is tailored according to needs.

In network communication, there are many communication methods based on TCP/IP protocol. This article uses Socket to realize data communication between server and client. Socket is a socket specification based on transport layer protocol, which defines the specification for communication between two computers. Socket shields the differences between the underlying communication software and the specific operating system, making communication between any two computers with TCP protocol software installed and socket specification implemented possible. When developing the socket program under ptCLinux system, TCP socket is used because it provides a reliable connection-oriented data transmission method, has error detection and correction mechanism, and provides a streaming data transmission method for both single datagram and data packet. The server first starts and performs initialization operation, creates a socket by calling the function socket(), then calls the function bind() to bind the socket to the local network address, and then calls the function listen() to convert the socket into a listening socket, and then calls the function accept() to wait for receiving the client's request. After the client calls the socket() function to establish a socket, it can call the connect() function to establish a connection with the server. Once the connection is established, the client and server can communicate by calling the read() and close() functions. After the data transmission is completed, both parties call the close() function to close the socket.

By jointly debugging the system, the tested data can communicate with the remote host computer without loss, in real time, and over long distances, and can receive the control instructions of the host computer, thus realizing the task of remote interaction of working status. The tester can edit the telemetry data through the host computer and check whether the received data is correct at any time.

This paper introduces the design and implementation of a protocol converter based on DSP+ARM architecture. It provides a detailed hardware platform structure design scheme and explains the implementation method of network programming based on embedded systems. The protocol converter implemented according to this scheme has the advantages of low cost, low power consumption, good versatility, and scalable and expandable functions.