Design of Reconfigurable Detection System Based on ARM and CPLD

Introduction
The reconfigurable design of the detection system is the development direction of detection technology. Reconfigurable design refers to the design method of using reusable software and hardware resources to flexibly change its own architecture according to different application requirements. For the detection system, reconfiguration can be divided into software reconfiguration and hardware reconfiguration. The detection system designed with hardware reconfiguration technology has hardware universality. By replacing each hardware module or configuring different software codes, different functions can be detected, thereby reducing the investment in hardware and software development and shortening the product development cycle.
This paper proposes a hardware reconfigurable design method for the detection system based on ARM embedded microprocessor and complex programmable logic device (CPLD). This structural detection system has the characteristics of small size, high integration, fast computing speed, large memory capacity and low power consumption of ARM microcontroller; it also has the powerful high-speed logic processing capability and convenient and flexible dynamic reconfigurability of CPLD. Combining the two can overcome the shortcomings of traditional detection instruments, and can hardwareize many complex real-time control algorithms, reduce the burden of MCU, and reduce the use of logic control chips. It has the outstanding advantages of strong reliability, good reusability and high cost performance.
1 Structure of the detection system
The reconfigurable detection system designed in this paper adopts ARM chip as the main controller and CPLD chip as the coprocessor to cooperate with the main controller.
1.1 Overall hardware structure of the detection system
The hardware structure of the controller is shown in Figure 1. The peripheral circuits of the ARM chip include reset circuit, real-time clock circuit, storage module, mass data storage module, communication module, LCD interface circuit and touch screen interface circuit. The storage module is composed of SDRAM and NOR FLASH. SDRAM is used as the memory of ARM to store dynamic data of the operating system and application program. FLASH stores the operating system image file and some constant parameters. The mass storage module provides an IDE/CF card interface, which can be directly connected to the hard disk and CF card as a mass storage medium for sampling data. The communication module is composed of RS-232, USB2.0 and Ethernet interfaces. One of them can be selected as the communication interface according to the actual situation. CPLD provides analog-to-digital conversion circuit control unit (ADC), programmable pulse generation circuit, sampling data self-storage logic control unit, digital input and output circuit (DI/DO), photoelectric encoder input circuit and PWM wave output circuit. ARM and CPLD are connected via a parallel bus.

Figure 1 Block diagram of reconfigurable detection system based on ARM9+CPLD
In the above structure, CPLD can be regarded as a high-speed peripheral of ARM. ARM indirectly operates some peripheral devices through CPLD, making full use of CPLD's high-speed logic processing capability to achieve real-time control of the entire detection process. ARM is only responsible for setting detection parameters and controlling the start and end of the detection process, which improves the real-time performance of the controller and enhances the compatibility and expansibility of the controller to peripherals.
In the above system design, we not only realize the modularization of hardware principle design, but also replace each module with a suitable chip according to actual needs to achieve the reconfigurability of the system. In the practice of production, maintenance and upgrading of detection instruments, we found that designing different modules into single-board form and then connecting them through agreed interfaces facilitates system upgrades and product serialization, and also brings great convenience to instrument maintenance. At the same time, it is easy to isolate the mutual interference of each module and improve the anti-interference and stability of the system. However, for a high-speed system, such a design will inevitably bring signal integrity problems. We will focus on the solution to this problem later.
1.2 Interface Design
Since the rationality of the bus interface design between ARM and CPLD will directly affect the performance of the controller and the reconfigurable characteristics of the system, the design of the parallel bus becomes a very critical issue. The bus includes the address bus (AB[0..23]), data bus (DB[0..15]), control bus, reset signal and multi-channel programmable I/O of the ARM chip. The advantage of this is that the CPLD chip is memorized, that is, ARM can control the operation of CPLD by accessing specific addresses and I/O ports, and can reset ARM and CPLD chips at the same time through a common reset signal, so as to avoid bus competition and risk. CPLD can also send interrupt requests to ARM through programmable I/O, waiting for ARM to process specific events. This interface not only retains the independence of the ARM control platform and the CPLD external unit, but also has very good versatility. General control platforms and logic control chips are suitable for this interface, so that we can build a suitable system according to different needs.
Similarly, the external interface design on the CPLD board is also very important, which directly determines the functions and applicability of the system. We have reserved 4 ADC control interfaces on the CPLD board, including sampling synchronization clock signals, sampling data transmission lines and multi-channel expansion I/O, which can realize simultaneous sampling of 4 ADs, automatic storage, and record the starting position and sampling length of the acquisition, and can also complete the control of programmable amplifiers and filters. Considering that a series of sampling storage chips SRAM with different capacities generally maintain pin compatibility, we designed SRAM on the CPLD board to increase the stability of the system. We try our best to ensure the versatility of other reserved interfaces, and consider the connection and installation of each module in the structural design.
2 Application Examples
Ultrasonic testing is one of the important methods of non-destructive testing, and is widely used in flaw detection of steel plates, forgings, welds, concrete, artificial graphite, etc. In recent years, the theory and methods of ultrasonic testing have made great progress, but in practice, there are still many key technologies that have not been broken through in both the implementation of instrument hardware and the update of software. The author uses the above system to design a one-transmit-two-receive acoustic wave detector. Its detection control unit is located in the CPLD chip. The ARM chip can complete the control of the entire detection process by accessing the memory of the CPLD. [page]

2.1 Chip Selection
ARM uses the EP9315 microcontroller with an embedded ARM920T core, and the CPLD uses the Alter MAX II series chip EPM1270. Among them, EP9315 has an operating frequency of up to 200MHz, 16KByte instruction cache, 16KByte data cache, and single/double precision integer and floating point processing capabilities. It also integrates a large number of applicable external interfaces, such as IDE interface, USB interface and LCD interface; EPM1270 CPLD contains 1270 logic elements and more than 100 available I/O pins. Each IO port can be configured to TTL, LVTTL, CMOS, LVCMOS and Schmitt trigger mode. The above two chips are low-cost and low-power chips.
2.2 Internal structure design of CPLD
In this system, ARM is the main chip, responsible for complex data processing, human-computer interaction, graphic display and interface communication tasks. How to reasonably design the external interface and internal structure of CPLD will directly affect the function and reconfigurability of the system. The internal structure of CPLD is shown in Figure 2. It includes a clock generator, four timing counting modules, a transmission pulse generation module, a sampling timing generation module, a photoelectric encoding counting module and an interrupt generator, which can perform closed-loop/open-loop detection.

Figure 2 CPLD internal structure Figure
2.3 Analysis of signal integrity issues in high-speed board-to-board design
In order to make the system architecture reconfigurable, the author designed the system into a multi-PCB structure, with the system board with ARM as the main chip as the main board and the expansion board with CPLD as the core as the backplane. Since this system is a high-speed system, such a design will inevitably bring signal integrity problems. The most important of these is that the long-distance transmission of the signal leads to a decrease in signal quality and the occurrence of the "ground bounce" phenomenon. The
backplane design will greatly increase the transmission distance of the signal, which greatly affects the quality of the signal. In the design, the author uses methods such as adding data buffers to the signal line for isolation and selecting source end resistance matching to solve the problem of effective signal transmission.
We establish the following ground bounce model diagram based on the actual situation, as shown in Figure 3. It can be seen from Figure 3 that when the logic gate of the ARM chip switches rapidly, a large transient current will be caused. Due to the existence of the distributed inductance Lg on the power connection line between the two boards, a serious "ground bounce" phenomenon will occur. According to the ground bounce voltage
V = Lg × dI/dt
, it can be seen that the ground bounce voltage is proportional to the distributed inductance and transient current on the power connection line. Therefore, we processed the power connection method between the two boards, increased the area of ​​the return wire, and minimized the length of the return wire to make the inductance on the return path as small as possible; at the same time, we added resistance to suppress transient current on the signal line. The test results show that this design better solves the power integrity problem.

Figure 3 Earth-bounce model

3 Conclusion
This paper introduces a design method of a reconfigurable detection platform based on ARM+CPLD structure, and develops a test prototype for steel plate, forging and foundation pile detection based on this method. This method cleverly combines ARM and CPLD technology in a modular way, so that the detection instrument built based on this method has the advantages of both ARM and CPLD, and realizes the hardware of some control algorithms. Compared with traditional MCU-based detection equipment, it has many advantages such as good real-time performance, high detection speed, fewer peripheral devices, good compatibility and scalability; and it has the reconfigurability of hardware solutions, which is more convenient for customers' application development and low cost. The field experiment has verified that the detection equipment has greatly improved the speed and intelligence of field detection. Because the design scheme has extremely flexible reconfigurability, it can be applied to other detection systems with slight modifications and expansions.

The author's innovation: A design method for a reconfigurable detection system based on ARM+CPLD structure was proposed. A new type of acoustic wave detector was developed based on this method, which improved the automation level of field testing.