Design of large capacity data acquisition system based on AVR microcontroller

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0 Introduction
The AVR series of single-chip microcomputers have been widely used for their powerful functions, high reliability, high speed, and low power consumption. However, the storage space of the AVR single-chip microcomputer itself is not large. For example, in a long-term or high-speed data acquisition system, the demand for data storage space is very large, and the space of the single-chip microcomputer itself is difficult to meet the storage requirements, so its role is limited in the case of large-capacity data acquisition. Therefore, expanding a storage chip based on the AVR single-chip microcomputer can solve the problem of its small storage capacity.
Flash memory is small in size, large in capacity, and can be randomly accessed, making it the best choice as an extended storage chip. The design uses the NAND type K9F5608UOM chip produced by sumsung as an extended storage.

1 Hardware Design
The paper designs a 5-channel A/D acquisition circuit and introduces how to realize large-capacity data acquisition in an actual circuit. Design requirements: 5-channel parallel acquisition circuit, A/D acquisition accuracy of 12 bits, acquisition speed of each channel is about 10 k/s, and effective acquisition time is about 10 minutes. From this we can get the required storage space size is about 3 M (10 × 5 x10 × 60 K), the data storage capacity of the general AVR microcontroller is far from reaching, so a FLASH chip is expanded as a data storage device.
The entire data control acquisition system consists of three modules, namely the data acquisition module composed of the MAX1304 analog-to-digital conversion chip, the data storage module composed of the K9F4G08UOM storage chip, and the system control module composed of the Atm-ega16L chip. The system design architecture is shown in Figure 1.

a.jpg


1.1 Introduction to system control chip
ATmage16L is an AVR microcontroller launched by ATMEL in the first quarter of 2002. It adopts RISC instruction system and Havard structure design, has high-speed processing capability close to 1MIPS/MHz, 16 k bytes of online programming FLASH, 512 bytes of EEPROM data storage, and 32 programmable bidirectional I/O ports for transmitting addresses and data. The chip pins are shown in Figure 2.

b.jpg


1.2 A/D chip interface design
MAX1304 is a programmable 12-bit precision serial output A/D conversion chip launched by MAXIM. It has 8 analog channel inputs, each with an independent sample-and-hold (T/H) circuit. The parallel sampling function greatly improves the sampling rate and can be used in high-speed data acquisition circuits. Its voltage input range is 0 to +5 V, and it has ±6 V fault protection, providing a good safety barrier for the circuit. The internal or external reference mode and the internal or external clock selection allow great flexibility in circuit design. The internal clock and internal reference mode are selected in this design (the typical circuit connection is shown in Figure 3). The data bit of MAX1304 is connected to the B and D expansion ports of ATmegal6L to realize the reading of collected data; its control bit is connected to the A expansion port of ATmegal6L to control AD ​​conversion, chip configuration and other operations. [page]

The high 8 bits of the 12 I/O ports of MAX1304 are connected to the 8 ports of PB respectively, and the low 4 bits are connected to the first 4 ports of PD. The high 8 bits D0~D7 can be configured to select the analog input channel to be started. When power is on, write the configuration register before starting the conversion bit CONVST (connected to PA4) to select the valid channel. When writing the configuration register, set the chip select CS (connected to PA3) and write enable WR (PA2) to low level, then load D0~D7 bits to the parallel bus, and then set WR to high level. The data is latched on the rising edge of WR. The conversion end bit EOLC (connected to PA0) indicates the end of conversion of all selected channels. At the falling edge of EOLC, set CS (connected to PA3) and read RD (connected to PA1) to low level to place the first conversion result on the parallel bus. Continuous low-level pulses of RD put the conversion results on the bus in sequence. After the last conversion result in the timing is read, additional read pulses can make the pointer point back to the first conversion result.
1.3 Flash chip interface design
K9F5608UOM 32M×8-bit flash memory is a large-capacity, high-reliability memory based on NAND technology produced by sumsung. The chip has a simple structure and only one storage body; the data read, write and erase speed is fast, and the average read speed per byte in page order is 50 ns, which is equivalent to the general SRAM; the interface circuit is simple, with 8-bit bidirectional I/O port, address, and data multiplexing; programming is simple, and the on-chip write operation controller automatically performs all write operations and erase functions, including providing necessary pulses, internal verification, etc., without the need for external controller considerations; data integrity is good, with hardware write protection function, and CMOS floating gate technology is used to increase its life (erasable 100,000 times), and data is stored for 10 years without loss. In this design, the data bit of Flash is connected to the C expansion port of ATme-gal6L, and the control bit is connected to the B and D expansion ports of ATmegal6L to realize data write operations.

c.jpg


As shown in Figure 4, the 8 I/Os of the Flash chip are connected to PC0~7 of ATmega16L as a data bus, which is used to input commands, addresses, and data, and output data in read operations. The busy indication (R/B) is connected to PD4, which indicates the device operation status. When a write, erase, or random read operation is performed, the indication is low level, and the indication is high level after the operation is completed. Read enable RE is connected to PD5, which controls the data in the chip to be placed on the I/O center line. The data is valid at its falling edge, and the internal column address is automatically increased by 1. Write enable WE is connected to PA5, which is used to control the command, address, and data to be written to the I/O port at its rising edge, and must be kept high during read operations. Chip select CE is connected to PD6, which is used for device selection control. During a read operation, if CE becomes high level, the device enters the standby state, and when the device is in a write operation or erase process, it is not affected by the high CE. The command latch enable CLE is connected to PA7, so that the input command is sent to the command register. When it becomes a high level, the command is latched into the command register through the I/O port at the rising edge of WE. The address latch enable ALE is connected to PA6, so that the input address is sent to the address register. When it becomes a high level, the address is latched at the rising edge of WE. Write protection WP provides protection against accidental erase and write operations caused by sudden changes in chip supply voltage. When WP is set low, the internal high-voltage source resets the chip, the pin state is uncertain, and it is in a non-operating state. Since this design only needs to write data to Flash, the write protection WP is connected to VCC to force a high level.

2 Software Design Process
The data acquisition module is responsible for digitizing the analog input of 5 channels and converting each analog quantity into a 12-bit digital quantity for parallel output. The function of the control module is to read and write the data converted by MAX1304 into the K9F4G08UOM storage module.

d.jpg


Figure 5 shows the entire software design process. When the MAX1304 is powered on, it starts to configure the register to select the first 5 analog channel inputs. At the rising edge of the first CONVST pulse, the 5 parallel sampling data begins to convert. When all the selected channel data are converted, EOLC will output a low level. You can query the port status to find out whether the conversion is completed. When the port level is high, continue to convert the next channel data; when it is low, ATmega16L configures the corresponding read port to the read state, reads this channel of data into the cache of ATmega16L, and controls the Flash chip to write the data in the cache into it. With the pulse signals of 5 RDs, the data of the 5 channels will be placed on the 12-bit I/O bus in turn. Therefore, the data collected in parallel can be written to the Flash by looping 5 times. Then enter the read and write operation at the next moment, and the whole process can be looped.

3 Conclusion
Through this 5-channel acquisition circuit, we can see that the actual interface design of the ATmega16L microcontroller and the 32M K9F5608UOM large-capacity Flash storage chip is very simple, and the operation is flexible and changeable. Based on the above design, the 5-channel can be expanded to within 8 channels (can be achieved by configuring the MAX1304 chip), realizing more channels of parallel acquisition, and the appropriate size of Flash chip can be selected according to the actual situation. This expandable acquisition circuit has a high cost-effectiveness, without the need to select a more expensive large-capacity control chip, and can be widely used in large-volume data acquisition and recording systems.

Reference address:Design of large capacity data acquisition system based on AVR microcontroller

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