Communication method of dual CPU system of 51 series single chip microcomputer

Introduction
This paper introduces a novel method to realize the dual CPU system of 51 series single-chip microcomputer. This method flexibly uses the ID working mode of 51 single-chip microcomputer, so that 51 single-chip microcomputer without HOLD function can directly communicate data through off-chip RAM. Not only the hardware and software implementation are relatively simple, the data transmission speed is fast, and no high-cost special devices are involved. It has a certain reference significance for the design of general 51 single-chip microcomputer system.

1 General method for implementing dual processors

① Use dual-port RAM. This method conveniently realizes communication between CPUs and has greater flexibility in selecting CPU interfaces; however, this method will increase the difficulty and cost of circuit design.
② Use I/O ports for parallel communication. This method uses I/O ports to transmit data and control transmission, so it occupies more I/O ports; and the control process involves two CPUs for communication, so the software design is relatively complex.
③ Use serial ports for communication. Using UART or I2C bus to contact CPU is also a common method. This method is simple to implement, but the transmission speed is slow.
④ Shared memory. There are actually two different implementations of shared memory. The first one is like the Neuron node chip of the LON network, which uses different timing to implement shared memory. This method must be made into a dedicated chip, and the CPU and RAM are packaged together, which is generally difficult to implement. The second one is like the 96 series microcontroller, which uses the HOLD line to suspend the bus of one of the microcontrollers first to use its memory. This method is simple and has a fast transmission speed. This method is often used to implement dual CPUs in CPU systems with HOLD function.
2 Use shared memory to implement dual CPU communication

Since the 51 single-chip microcomputer does not have a HOLD function, it is generally not possible to use the shared memory method to achieve dual CPU communication. Here is a method that enables a general 51 single-chip microcomputer to achieve dual CPU communication using shared memory. This method has a simple circuit and is easy to implement in software and hardware; it has a fast data transmission speed and occupies less system resources (it does not use the I/O port to transfer data, but uses a part of the address space as the medium for data transmission), and can give full play to the role of dual CPUs. The following is a detailed introduction to this method.

2.1 Basic Design Scheme
First, machine A allocates a portion of the address space of the off-chip RAM as a dedicated channel for data transmission (generally, the high-end address space can be used); at the same time, this address space is mapped to the same size of the off-chip RAM address space of machine B that receives the data (machine B can directly access it). When the two sides need to transfer data, machine A directly reads and writes data to this address. Before reading and writing data, the two sides must communicate first and make preparations for data transmission.

The data lines on both sides should be separated by switch gate circuits, which can be tri-state gates. The address lines are also arranged by the designer, and the A side is directly mapped to the specific off-chip RAM address of the B side through the switch gate circuit. Because the A side needs to read and write data on the B side, the read and write selection signal of the A side to the off-chip RAM must also be connected to the read and write end of the B side through the switch. Before sending data, these switch gate circuits must be turned on. In this way, the A side can read and write data in the off-chip RAM of the B side.

Finally, there is an important task. The CPUs on both sides have their own independent work and run programs on their own data lines and address lines independently. To share the RAM of machine B to achieve communication, machine B must hand over the bus control during the transmission of communication data. However, the 51 microcontroller does not have the HOLD function of the 96 microcontroller. How can machine B hand over the bus control? Other methods are needed here. The 51 series microcontroller itself has an ID working mode (idle state), and the ID mode can be awakened by interrupts. We can use the ID working mode to suspend machine B, so that the CPU of machine A can access data on the side of machine B.
2.2 Specific implementation method
Figure 1 is a dual-machine system composed of two 51 microcontrollers. We divide the ordinary off-chip RAM address addressing space of machine A on the left into two different areas: 0000H~7FFFH and 8000H~0FFFFH. Among them, 0000H~7FFFH can be used as ordinary off-chip RAM space, and 8000H~0FFFFH can be used as a data transmission channel. Here, we map the off-chip RAM addressing space of 8000H~803FH to the address space of 0000H~003FH of the right-hand machine B. (In fact, any address above 8000H of machine A will be mapped to the corresponding 0000H~003FH space of machine B. For simplicity, only the highest address line of machine A is directly selected, and it is agreed that the communication data of machine A is written to 8000H~803FH.) Therefore, the lower six address lines of machine A are connected to the lower six address lines of machine B through 74ALS373. At the same time, the read and write control lines are also connected. The data lines on both sides are connected through 74ALS245 for bidirectional data transmission. When no data is transmitted, P1.7 of machine B is high, 74ALS373 is in high impedance state, and 74ALS245 is also in high impedance state because it is not selected by the address line of machine A. The CPUs on both sides can run programs in their own space and remain relatively independent. The P1.0 of MCU A is connected to the INT0 pin of MCU B, which can notify MCU B to process the transmitted data. At the same time, the interrupt can be used to wake up MCU B in the ID state. When transmitting data, P1.7 of MCU B is low level, turning on 74ALS373. At the same time, P1.7 of MCU B is also connected to the INT0 port of MCU A to notify MCU A that it can start sending or fetching data. The highest address line A15 of MCU A is used as the data selection signal, so that MCU A can read and write the data in the RAM of 0000H~003FH address space of MCU B. The data transmission direction is controlled by the P1.6 pin of MCU B.
When machine A wants to transfer data to machine B, it first outputs a falling edge pulse to the INT0 port of machine B through P1.0 to notify the MCU B. The interrupt service program of machine B determines that machine A wants to send data, and uses the instruction
MOV DPTR, #003FH
MOV A, #0FFH
MOVX @DPTR 0FFH
to set the address line to 003FH and the P0 port to FFH. Why do we need to do this? Because after machine B sets the address line to 003FH, it enters the ID state, and the address line will remain in this state, so machine A can control the lower six address lines of machine B; at the same time, the upper ten address lines of machine B remain "0", which ensures that the data of machine A is mapped to the address space of machine B from 0000H to 003FH. Machine B writes FFH to the data line to ensure that the P0 port is set to "1". After entering the ID working mode, the P0 port (that is, the data line) will also maintain this state to ensure that the data on the machine A side is written smoothly. Then, the P1.6 pin of machine B outputs a high level and sets the data transmission direction from machine A to machine B. Finally, machine B sends a falling edge pulse at the P1.7 pin to interrupt and notify machine A that it can send data. At the same time, it maintains a low level, turns on 74ALS373, and then executes
ORL PCON.0,#00000001B
enters the ID state. The INT0 interrupt service program of machine A sends the data from 8000H~803FH. After sending, a falling edge pulse is sent to the INT0 terminal of microcontroller B through P1.0 of machine A to wake up machine B. The INT0 interrupt service program of machine B determines that the data has been transmitted and processes the received data.
Similarly, when machine B wants to send data to machine A, it first writes the data to 0000H~003FH, and finally writes FFH to 003FH to complete the correct setting of the address line and data line. The P1.6 pin must also be set to a low level to control the data from machine B to machine A. Then a falling edge pulse is sent to P1.7 of machine B to trigger the INT0 interrupt of machine A. At the same time, P1.7 remains at a low level, opens the three-state gate, and then enters the ID state. The INT0 interrupt service program of machine A determines that machine B wants to send data and has already done so. After being prepared, the data is fetched from 8000H~803FH (of course, the data in 803FH is invalid). After fetching, machine A sends a "1" falling edge pulse to the INT0 terminal of microcontroller B through P1.0 to wake up machine B and let machine B continue to run the program.
The INT0 interrupt service program of machine B has to handle several different transactions and has several branches. If machine B transmits data to machine A, machine B's INT0 does not need to do any substantial work, just exit the interrupt and continue to run the main program; if machine A transmits data to machine B, before transmitting the data, machine B's INT0 must be prepared for the data transmission and set machine B to ID state. After the data is transmitted, machine B's INT0 processes the data. Here, two flags, data transmission direction and data transmission status, must be set to guide the program to run correctly. Machine A's INT0 can transmit or read data according to the data transmission direction flag. No specific program will be written here