Design of signal processing system based on dual single chip microcomputer

When the detection and control system processes a large amount of data and multiple information, only one single-chip microcomputer often cannot meet the system's real-time and scalability requirements, and the processing time is long. For example, in the process of collecting liquid level information, the single-chip microcomputer must perform A/D conversion and data processing at equal time intervals. In order to achieve high-throughput liquid operations, the liquid operation platform is usually equipped with multiple pipette needles to perform liquid operations at the same time and collect multiple liquid level information. Therefore, a signal processing system design based on dual single-chip microcomputers is proposed here. The system uses a single-chip microcomputer (AT89S51) as the core device, and two AT89S51 single-chip microcomputers are used as dual cores to share the tasks of the entire detection unit.

1 System Hardware Circuit Design

The overall design of the signal processing system is as follows: MCU 1 performs A/D conversion at regular intervals and stores the conversion results in an external data memory; MCU 2 reads the conversion results in the data memory and transmits them to the computer through the serial port, and is also responsible for starting or stopping the A/D conversion work of MCU 1 after the system receives a start or stop command. Figure 1 is a hardware structure block diagram of the signal processing system.

Figure 1 Hardware structure diagram of the signal processing system

According to the above design scheme, the system hardware is divided into the following modules:

1.1 A/D conversion module design

Since the AT89S51 microcontroller does not have an A/D conversion module, a device with A/D conversion function is required in the acquisition system. Here, ADC0832 is used. ADC0832 is an 8-bit resolution, dual-channel A/D converter produced by National Semiconductor Corporation. Its main features are as follows: the input and output levels are compatible with TTL/CMOS; the input voltage is between 0 and 5 V when powered by 5 V; the operating frequency is 250 kHz, and the conversion time is 32 μs; the general power consumption is only 15 mW.

The A/D conversion module design uses the following pins of ADC0832: Pin 1 (CS) is the chip select enable signal terminal, connected to the P3.4 pin of the AT89S51 microcontroller. Pin 2 (CH0) and Pin 3 (CH1) are two analog input channels. Since the detector only uses one capacitive sensor, only Pin 3 is used as the analog input here. Pin 5 (DI) is the data signal input terminal, responsible for selecting channel control. Pin 6 (DO) is the data signal output terminal, responsible for outputting the converted data. Since Pins 5 and 6 are not valid at the same time during communication, and are a bidirectional interface with the microcontroller, these two pins are connected together during use and connected to the P1.1 pin of the microcontroller; Pin 7 (CLK) is the chip clock input, connected to the P1.0 pin of the microcontroller, as shown in Figure 2.

Figure 2 Signal processing unit circuit

1.2 Storage Module Design

After comprehensive consideration of memory performance, price, purchasing conditions and other factors, the system design uses Cypress's CY7C132. This device is a 2 Kx8-bit high-speed dual-port static read-write memory. The two ports can independently access any storage unit in the memory. The CY7C132 has two sets of symmetrical signal lines, that is, each port has independent address lines, data lines, control lines and communication signal bits. The access time is 25 to 55 ns, and it is automatically in a low-power state when not selected. It operates asynchronously, has input and output tri-states, and is compatible with TTL levels.

CY7C132 allows two CPUs to read any storage unit at the same time (including reading the same address unit at the same time), but does not allow simultaneous writing or reading and writing the same address unit. The arbitration logic (busy logic) circuit is introduced in the dual-port RAM to solve this problem: when the left and right processors write or read and write the same address unit at the same time, the first stable address port is given priority to read and write through the arbitration logic circuit, and at the same time, the internal circuit makes the BUSY signal of the other port valid, and prohibits the other party from accessing it internally until the operation of this port is completed. The BUSY signal can be used as an interrupt source to indicate that this operation is illegal. It should be noted that this method may reduce program efficiency when the CPU is waiting for insertion, and cannot be used in situations where insertion interrupts are frequently generated.

The system design uses CY7C132 with an access time of 55 ns. The slave microcontroller works at the μs level, and the master microcontroller works at the ms level. The probability of both parties reading the dual-port RAM at the same time is small, and the above conflict solution can meet the actual needs. After the master and slave microcontrollers start working, in order to prevent the master microcontroller from reading empty, that is, the first write time of the slave microcontroller is later than the first read time of the master microcontroller, the first address of the memory is set to the start flag bit, and the master microcontroller reads and writes this state to determine whether to read the next storage bit.

2 Specific circuit design

According to the overall structure block diagram and functional design of the above system, the circuit schematic diagram of the signal processing system is drawn, as shown in Figure 2.

The control or detection work of the microcontroller is realized through the I/O pins. In microcontroller 1 (U1), the PO and P2 pins as well as the P3.6 and P3.7 pins are used to exchange data with the external data memory CY7C132; the P1.0, P1.1 and P3.4 pins are connected to the A/D converter ADC0832 to control the A/D conversion operation and read the conversion results: the P3.2 (external interrupt 0) pin communicates with the pin P1.0 of microcontroller 2 (V2). The use of the I/O pins of microcontroller 2 is similar to that of microcontroller 1. It is particularly important to point out that the P1.2 pin of microcontroller 2 is connected to the BUSY pin of CY7C132; and P3.0 and P3.1 are serial communication pins connected to MAX232.

CY7C132 is a dual-port RAM, but the connection method of the address line, data line and control line at either end is almost the same as that of general RAM. The address lines and data lines of the two microcontrollers and CY7C132 are connected in the same way. Taking microcontroller 1 as an example, the internal storage space of CY7C132 is 2KB, so its address space is 0000H~07FFH. The I/O port of the microcontroller needs to provide 11 address lines, and in addition to the P0 port, the P2.0, P2.1, and P2.2 ports are also required. This system design only uses the external RAM of the microcontroller AT89S51, so there is no chip select problem. The line selection method is used here, and P2.3 is directly connected to the CS of CY7C132.

In addition, for the following reasons, microcontroller 1 and microcontroller 2 use external crystal oscillators with different frequencies: 1) The frequency supported by microcontroller AT89S51 is limited, and the selected crystal oscillator frequency must meet the requirements; 2) Since AT89S51 uses the machine cycle as its working basis, when using an external oscillator circuit, the microcontroller uses the value obtained by dividing the crystal oscillator frequency by 12 as the machine cycle, so when microcontroller 1 needs a timer, the crystal oscillator frequency must be convenient for setting the timer; 3) Microcontroller 2 needs to communicate with the computer via serial port, and the crystal oscillator frequency must be convenient for setting the baud rate in serial port communication. Therefore, the crystal oscillator frequencies of microcontroller 1 and microcontroller 2 were selected as 12 MHz and 11.0592 MHz respectively.

3 System Software Design

The software design of this system uses assembly language. The advantages of assembly language are: the program written has small storage space, fast running speed and high program efficiency. In addition, the program written in assembly language can directly manage and control hardware devices. The program written in assembly language cannot be directly used by the microcontroller and must be compiled using a compiler. This system uses the Keil C5l V7.09 evaluation version.

3.1 MCU main program

MCU 1 uses 20H.1 of the internal RAM as the A/D conversion flag. When the flag is set to 1, the A/D conversion subroutine in the main program will not run; when the flag is set to 0, the A/D conversion subroutine can be executed. The main program execution process of MCU 1 is shown in Figure 3(a). MCU 2 uses 20H.1 of the internal RAM as the program start flag. When the flag is set to 1, the main program will not run; when the flag is set to 0, the main program can be executed. After the main program starts running, data is read from the external data register, then the serial port interrupt is turned off, data is written to the serial port through query mode, and then the serial port interrupt is turned on. The main program execution process of MCU 2 is shown in Figure 3(b).

Figure 3 Main program flow chart

3.2 Digital filtering subroutine

The principle of arithmetic mean filtering is to find a value y(k) for n consecutively sampled data so that the sum of the squares of the errors between the value and the sampled value is minimized.

The mean value filtering formula for finding the extreme value of a univariate function is:

Where y(k) is the average value of N sampling values ​​at the kth sampling, and X(i) is the i-th sampling value.

Arithmetic mean filtering is suitable for situations where the measured signal fluctuates around a certain digital range. This method spreads the impact of interference to each measured value. The number of samples n determines the ability to resist interference. The larger the n, the better the anti-interference performance. However, if the n value is too large, the sensitivity of the system will decrease. Arithmetic mean filtering has a good inhibitory effect on periodic interference, but has little effect on pulse interference.

The median filter algorithm samples a certain measured parameter n times continuously (usually n is an odd number). The n sampling values ​​are arranged in order of size, and the middle value is taken as the current sampling value. The median filter algorithm can effectively overcome the fluctuation interference caused by accidental factors. For measured parameters that change slowly, such as temperature and liquid surface, a good filtering effect can be achieved. The flow chart of the median filter subroutine and the arithmetic mean filter subroutine is shown in Figure 4.

4 Experimental data

During the experiment, the auxiliary tools of the test platform include the WJ7103 DC regulated power supply that can provide ±5 V output and the AFG3021 function generator of Tektronic, USA. First, the DC signal generated by the signal function generator is transmitted to the industrial computer through the signal processing unit circuit board; secondly, the measured data is displayed through the serial port assistant and stored in the industrial computer in text format (txt); finally, the measured data is displayed in the form of images and recorded in decimal format through MATLAB software.

Under the condition of 0 V signal input, the sampling results of the signal processing unit (random sampling 1000 times) are shown in Figure 5. (1), (2), and (3) in the figure respectively represent the output results obtained by the single chip computer 1 without using the digital filtering algorithm, using the median filtering algorithm, and using the arithmetic mean filtering algorithm. Ideally, the sampling value should be 0, but there is an error between the recorded sampling result and the ideal value.

Under the condition of 2 V signal input, the sampling result of the signal processing unit (random sampling 1000 times) is shown in Figure 6. (1), (2), and (3) in the figure respectively represent the output results obtained by the single chip computer 1 without using the digital filtering algorithm, using the median filtering algorithm, and using the arithmetic mean filtering algorithm. In the sampling result, under ideal conditions, the sampling value should be 102.

Figure 6 2V DC signal input sampling results

By analyzing the sampling results under two different conditions, it can be concluded that when using the filtering algorithm, the sampling results of the detection system will be more concentrated near the ideal value, but the error of the sampling result has not been eliminated, and the error has obvious randomness. According to the error theory, this type of error should belong to the undetermined system error.

It can be seen from Table 1 that when the arithmetic mean filtering algorithm is used, the accuracy of the sampling result of the signal processing unit can be improved. Therefore, the arithmetic mean filtering algorithm is used as the digital filtering algorithm of the single chip microcomputer.

The system is used for signal processing of the liquid level detection system to verify the feasibility of the system. Under ideal conditions, the liquid level signal will change according to a linear law. In addition, the capacitance detection circuit designed according to the liquid level detection principle also reflects the relationship between the capacitance value and the voltage value in a linear law. Therefore, the signal that changes in a linear law is an important indicator for testing the detection system.

Under the condition of using a function generator to simulate a linear change signal, the function generator is set as follows: the output of the sawtooth wave, the rising interval accounts for 100%, the output frequency is 1 Hz, the lower offset is 0 V, and the Vp-p is 2 V. The sampling frequency of the signal processing unit is set to 100 Hz, and 4 points are used for arithmetic mean filtering. The line graph of the sampling results of 1,000 random samplings is shown in Figure 7. From the sampling results, it can be seen that after being processed by the filtering algorithm, the signal processing unit can obtain better sampling results.

5 Conclusion

This paper completes the design of a signal processing system based on dual single-chip microcomputers. ADC0832 performs A/D conversion on the signals to be collected. The two single-chip microcomputers can read any storage unit of the independent external memory at the same time, and send the data read from the memory by single-chip microcomputer 2 to the computer through the serial port. The different crystal oscillator frequency settings of the two single-chip microcomputers are convenient for different working states. The experiment shows that using dual single-chip microcomputers as the core of the signal processing system has the advantages of easy real-time control and easy system expansion, which is a development direction of information processing in the future.