ARM processor base Cortex-M4

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Startup Process

Processor operating mode

Processor modes are divided into thread mode and processing mode; software execution is divided into privileged mode and non-privileged mode (user mode); the stack is divided into MSP Main stack and PSP Program stack.

In process mode, it is always privileged and always uses the main stack.

In thread mode, you can set whether it is privileged or user (CONTROL Reg[0]), and you can set whether to use the main stack or the program stack (CONTROL Reg[1]).

PM0214, Programming manual, STM32F3 and STM32F4 Series Cortex ® -M4 programming manual, p16

The processor modes are:
Thread mode: Used to execute application software.
The processor enters Thread mode when it comes out of reset.
The CONTROL register controls whether software execution is
privileged or unprivileged, see CONTROL register on page 24.
Handler mode: Used to handle exceptions.
The processor returns to Thread mode when it has finished exception
processing.
Software execution is always privileged.

The privilege levels for software execution are:

Unprivileged: Unprivileged software executes at the unprivileged level and:
• Has limited access to the MSR and MRS instructions, and cannot
use the CPS instruction
• Cannot access the system timer, NVIC, or system control block
• Might have restricted access to memory or peripherals
• Must use the SVC instruction to make a supervisor call to transfer control to privileged software
Privileged: Privileged software executes at the privileged level and can use all the
instructions and has access to all resources.
Can write to the CONTROL register to change the privilege level for
software execution.

In an OS environment, it is recommended that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.

In an operating system environment, it is recommended that the thread mode use the program stack PSP, and the kernel and exception processing use the main stack MSP.


After reset, the processor is in thread mode + privilege level;

Privileged to User: Code at the privileged level can enter the user level by setting CONTROL[0].

User to privileged: A user-level program cannot simply try to rewrite the CONTROL register to return to the privileged level. It must first "appeal": execute a system call instruction (SVC). This triggers an SVC exception, which is then taken over by the exception service routine (usually part of the operating system). If entry is granted, the exception service routine modifies the CONTROL register to re-enter the privileged level in user-level thread mode. In fact, the only way from user level to privileged level is through exceptions.

By default, Thread mode uses the MSP.
To switch the stack pointer used in Thread mode to the PSP
(1) use the MSR instruction to set the Active stack pointer bit to 1, CONTROL[1] = 1
(2) perform an exception return to Thread mode with the appropriate EXC_RETURN value


When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB instruction execute using the new stack pointer.


The thread uses the main stack MSP by default. If you want to use the program stack PSP, there are two conversion methods.

Common assembly instructions

PUSH POP

PUSH{cond} reglist
POP{cond} reglist

• PUSH stores registers on the stack in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest
numbered register using the lowest memory address.
• POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. (Programming manual p77)

push {r0, r1}, because ARM uses Full Descending stack, that is, the stack pointer points to the last data, and the stack address decreases. Therefore, the order of pushing this sentence into the stack is r1 first, then r0, to meet the above description.

MSR

Move the contents of a general-purpose register into the specified special register.

Copy general Reg to special S reg

• 'Rn' is the source register.
• 'spec_reg' can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

The register access operation in MSR depends on the privilege level. Unprivileged software can only access the APSR

Except APSR, operations on other special registers must be performed in privileged mode, similar to the MRS instruction.

CPS

Change processor state.

CPSID i ; Disable interrupts and configurable fault handlers (set PRIMASK)
CPSID f ; Disable interrupts and all fault handlers (set FAULTMASK)
CPSIE i ; Enable interrupts and configurable fault handlers (clear PRIMASK)
CPSIE f ; Enable interrupts and fault handlers (clear FAULTMASK )


Reference address:ARM processor base Cortex-M4

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