u-boot-2011.06 supports NandFlash reading and writing in the transplantation based on s3c2440 development board

Since the NandFlash controllers of s3c2410 and s3c2440 are different, the s3c2440_nand.c file cannot be directly applied and needs to be modified appropriately. The main modification is the related registers of s3c2440.

First, redefine the registers to be used, remove the macro definitions between lines 27 to 37 in the original text, and change them to the following form:

#define S3C2440_NFCONT_SECCL (1<<6)

#define S3C2440_NFCONT_MECCL (1<<5)

#define S3C2440_NFCONT_INITECC (1<<4)

#define S3C2440_NFCONT_nCE (1<<1)

#define S3C2440_NFCONT_MODE (1<<0)

#define S3C2440_NFCONF_TACLS(x) ((x)<<12)

#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)

#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)

#define S3C2440_ADDR_NALE 0x08

#define S3C2440_ADDR_NCLE 0x0C

Then modify the s3c2440_hwcontrol function and board_nand_init function, and keep other functions unchanged.

The board_nand_init function is mainly used to initialize NandFlash. The modifications to it are the registers NFCONF and NFCONT. The following is the modified board_nand_init function, where the red marked parts are the modified parts:

int board_nand_init(struct nand_chip *nand)

{

u_int32_t cfg;

u_int8_t tacls, twrph0, twrph1;

struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();

struct s3c2440_nand *nand_reg = s3c2440_get_base_nand();

debugX(1,"board_nand_init()n");

writel(readl(&clk_power->clkcon) |(1 << 4), &clk_power->clkcon);

/* initialize hardware */

#ifdefined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)

tacls = CONFIG_S3C24XX_TACLS;

twrph0 = CONFIG_S3C24XX_TWRPH0;

twrph1 = CONFIG_S3C24XX_TWRPH1;

#else

tacls = 2;

twrph0 = 3;

twrph1 = 1;

#endif

cfg = S3C2440_NFCONF_TACLS(tacls - 1);

cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);

cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);

writel(cfg,&nand_reg->nfconf);

cfg = S3C2440_NFCONT_SECCL;

cfg |= S3C2440_NFCONT_MECCL;

cfg |= S3C2440_NFCONT_MODE;

writel(cfg,&nand_reg->nfcont);

/* initialize nand_chip data structure */

nand->IO_ADDR_R = (void*)&nand_reg->nfdata;

nand->IO_ADDR_W = (void*)&nand_reg->nfdata;

nand->select_chip = NULL;

/* read_buf and write_buf are default */

/* read_byte and write_byte are default*/

#ifdefCONFIG_NAND_SPL

nand->read_buf = nand_read_buf;

#endif

/* hwcontrol always must be implemented*/

nand->cmd_ctrl = s3c2440_hwcontrol;

nand->dev_ready = s3c2440_dev_ready;

#ifdefCONFIG_S3C2440_NAND_HWECC

nand->ecc.hwctl = s3c2440_nand_enable_hwecc;

nand->ecc.calculate = s3c2440_nand_calculate_ecc;

nand->ecc.correct = s3c2440_nand_correct_data;

nand->ecc.mode = NAND_ECC_HW;

nand->ecc.size =CONFIG_SYS_NAND_ECCSIZE;

nand->ecc.bytes =CONFIG_SYS_NAND_ECCBYTES;

#else

nand->ecc.mode = NAND_ECC_SOFT;

#endif

#ifdef CONFIG_S3C2440_NAND_BBT

nand->options = NAND_USE_FLASH_BBT;

#else

nand->options = 0;

#endif

debugX(1, "end ofnand_initn");

return 0;

}

Finally, modify the s3c2440_hwcontrol function, which is used to write commands and write addresses to NandFlash:

static void s3c2440_hwcontrol(structmtd_info *mtd, int cmd, unsigned int ctrl)

{

struct nand_chip *chip =mtd->priv;

struct s3c2440_nand *nand = s3c2440_get_base_nand();

debugX(1,"hwcontrol(): 0x%02x 0x%02xn", cmd, ctrl);

if (ctrl &NAND_CTRL_CHANGE) {

ulong IO_ADDR_W = (ulong)nand;

if (!(ctrl &NAND_CLE))

IO_ADDR_W|= S3C2440_ADDR_NCLE;

if (!(ctrl &NAND_ALE))

IO_ADDR_W|= S3C2440_ADDR_NALE;

if(cmd == NAND_CMD_NONE)

IO_ADDR_W = &nand->nfdata;

chip->IO_ADDR_W= (void *)IO_ADDR_W;

if (ctrl &NAND_NCE)

writel(readl(&nand->nfconf)& ~S3C2440_NFCONT_nCE,

&nand->nfconf);

else

writel(readl(&nand->nfconf)| S3C2440_NFCONT_nCE,

&nand->nfconf);

}

if (cmd != NAND_CMD_NONE)

writeb(cmd, chip->IO_ADDR_W);

}

In this function, in addition to modifying the register value and setting the IO port for writing commands and addresses, we also added the if (cmd == NAND_CMD_NONE) judgment statement. Without this judgment statement, data cannot be written into NandFlash. Although the system will not prompt any errors and display "OK", the data is not actually written. Therefore, this statement must be added. This is because after writing the command and address, the address of the IO port must be reset to the register NFDATA.

It should be noted that since the system does not define CONFIG_S3C2410_NAND_HWECC, we will not modify the s3c2440_nand_enable_hwecc function, s3c2440_nand_calculate_ecc function and s3c2440_nand_correct_data function for the time being.

We burn the compiled u-boot.bin file into norflash and use the relevant commands of NandFlash to verify:

U-Boot2011.06 (Aug 10 2011 - 23:16:25)

DRAM: 64 MiB

Flash: 2MiB

NAND: 256 MiB

***Warning - bad CRC, using default environment

In: serial

Out: serial

Err: serial

Net: CS8900-0

ZHAOCJ2440# nand info

Device 0: nand0, sector size 128 KiB

ZHAOCJ2440# nand device 0

ZHAOCJ2440# nand erase 0x100000 0x300000

NANDerase: device 0 offset 0x100000, size 0x300000

Erasingat 0x3e0000 -- 100% complete.

OK

ZHAOCJ2440# nand write 0 0x100000 0x300000

NANDwrite: device 0 offset 0x100000, size 0x300000

3145728 bytes written: OK

ZHAOCJ2440# nand read 0x30004000 0x100000 0x300000

NANDread: device 0 offset 0x100000, size 0x300000

3145728 bytes read: OK

ZHAOCJ2440#md.b 0

00000000:13 00 00 ea 14 f0 9f e5 14 f0 9fe5 14 f0 9f e5 ............

00000010:14 f0 9f e5 14 f0 9fe5 14 f0 9f e5 14 f0 9fe5 ............

00000020:e0 01 00 00 40 02 00 00 a0 0200 00 00 03 00 00 ....@........

00000030:60 03 00 00 c0 03 00 00 20 04 0000 ef be ad de `....... .......

ZHAOCJ2440# md.b 0x30004000

30004000:13 00 00 ea 14 f0 9f e5 14 f0 9fe5 14 f0 9f e5 ............

30004010:14 f0 9f e5 14 f0 9fe5 14 f0 9f e5 14 f0 9fe5 ............

30004020:e0 01 00 00 40 02 00 00 a0 0200 00 00 03 00 00 ....@.......

30004030:60 03 00 00 c0 03 00 00 20 04 0000 ef be ad de `....... .......

After power-on, NAND shows 256MiB, indicating that the system can correctly identify NandFlash. Then we write the data in SDRAM to NandFlash, and then read the data in NandFlash. By comparing it with the original SDRAM data, we can see that the contents of the two data segments are consistent, so we can conclude that the transplanted u-boot can correctly read and write NandFlash.

In addition, if you want to know more about the NandFlash on the development board, you can change MTDDEBUG in line 2676 of drivers/mtd/nand/nand_base.c to printf, and then remove MTD_DEBUG_LEVEL0 in the line. After power-on, the following content will be displayed:

U-Boot2011.06 (Aug 10 2011 - 23:55:48)

DRAM: 64 MiB

Flash: 2MiB

NAND: NAND device: ManufacturerID: 0xec, Chip ID: 0xda (Samsung NAND 256MiB 3,3V 8-bit)

256 MiB

***Warning - bad CRC, using default environment

In: serial

Out: serial

Err: serial

Net: CS8900-0