How to read the timing diagram--Detailed explanation of nand flash read operation

This article does not introduce the physical structure of nand flash and some basic knowledge about nand flash. You need to at least understand the physical structure of the nand flash you have and some basic knowledge such as read and write commands.

To get a rough idea of ​​the operation, you need to at least read the description of the nand flash control registers in s3c2440.

Since I have not received any specialized knowledge in this area, the following introduction is based on my experience.

Here I use K9F2G08-SCB0 nand flash to introduce the reading of timing diagram. Different chips may have different operation timings, and the read commands may also be slightly different.

Of course, sometimes, like NAND flash, the s3c2440 has its controller's peripherals integrated inside. As for the detailed timing of read and write operations (such as CLE/ALE setup time, write pulse width, data setup and hold time, etc.), it is not a big problem if you don't understand it in the early stage.

Because the nand flash controller inside the s3c2440 does most of the work, all you need to do is basically set a few timing parameters, and then the nand flash will automatically handle these details.

Of course, if the processor does not have an integrated nand flash controller, then you have to write the timing operations yourself. So it is always good to understand the lowest level timing operations.

But at a higher level, such as the timing of the steps in read and write operations (for example, for a read operation, you need to enable the chip select, then send a command, then send an address, and then send another command if necessary, then you need to wait for the operation to complete before reading the data).

If you don't understand this, how can you operate the device?

In other words, S3C2440 can be said to have done all the subtle operations in each step for you after you set a few time parameters. (For example, to write a command, you only need to write a command to the corresponding register, and the CPU will coordinate the pins to send it.

Adaptive signals to implement write command operations).

All we need to do is combine these steps: write command, write address, wait for operation to complete, etc., to complete a read operation.

As mentioned above, although we don't need to write the most detailed timing of each step, understanding it will make you more clear about the underlying details of each operation step.

Let's first look at the timing of a command latch. That is, isn't there a write command step in the read nand flash operation mentioned above? So how is this step implemented specifically?

First of all, we must select the nand flash chip. Only by selecting the chip can it work.

NAND flash uses ALE/CLE (high level is valid) to distinguish whether the data on the data line is a command (CLE is valid), an address (ALE is valid) or data (both CLE/ALE are invalid).

Since this is a write command, CLE must be valid (high level) and ALE must be invalid (low level).

Since the command is written to the nand flash, there must be a write cycle. We need to pay attention to whether the write is valid on the rising edge or the falling edge.

The timing diagram is as follows:

1 Here is the command latch timing, so we should pay attention to the timing when CLE is high. (Write command, when CLE is valid (high level), it indicates the current data, which is actually the command) ALE must be low at this time, so we don't need to care about it.

2 Therefore, when CLE is low, most of the other pins are shaded gray, which means we do not need to care about the levels of these pins during this period.

3 So when is this data read by the nand flash? Notice that the nWE signal has a vertical line running through all other pin timings on the rising edge (this seems to be called the lifeline? I don’t know either)

This means that the written data (commands are also data, but they can be distinguished by the validity of CLE) is valid on the rising edge of WE.

That is to say, although WE is valid at a low level, it does not mean that the command is latched (that is, the command is truly obtained) as soon as WE becomes a low level. Instead, the command is truly latched at the rising edge of WE.

Knowing the above three points, we have a rough idea, and the remaining figures only have the txx numbers. Obviously, it refers to time, but what time does it refer to?

It refers to the time between the two vertical lines on both sides of the arrow. (There are small vertical lines at the transition edge of each signal)

The rest is what these times represent. There is nothing difficult here. Newcomers may not understand it because they have never been exposed to it before. (Just like when we first learned microcontrollers, we didn’t understand a lot of things because we had never been exposed to it before.)
These time labels are explained in the front of the data sheet .

For example, from the data sheet we can see tCLS and tCLH, which represent the CLE setup time and the CLE signal hold time.

To put it simply, you can understand that if I let the CLE pin become a high level, it must give the human some time to become a high level. It can't become a high level instantly.

However, we can see more clues from the timing diagram. Didn’t we say before that there is a vertical line on the rising edge of WE that is the longest and runs through other signal lines? We say that it indicates that data (commands are also data)

It is latched on the rising edge. On the rising edge of WE, the command data I write to the data line is actually latched (received), but we noticed that the CLE signal is valid before the rising edge of WE.

So we say that the tCLS time during which CLE is valid before the command data is actually latched is called the CLE signal setup time.

After the WE rising edge, the command has been accepted, but at this time CLE can actually become invalid because the command has been obtained.

But it does not end immediately, but ends after Tclh time. So we call this time tCLH the CLE hold time.

Then according to the instructions in the manual, tCS represents the chip select signal setup time, and tCH represents the chip select signal hold time

tDS represents data setup time, tDH represents data hold time

Here we see a small rule. In the data sheet, the time ending with S usually refers to the setup time, and the time ending with H refers to the hold time.

The command latch timing is analyzed here. Let's look at the address latch timing diagram. This diagram is a bit complicated.

Because the characteristic of NAND flash is that the address cycle usually requires several times, that is, one address is sent several times

Then give the description of the corresponding time number in the data sheet

We also follow the steps analyzed above

1 Here is the address latch timing, so we should pay attention to the timing when ALE is high. (Write command, when ALE is valid (high level), it indicates that the current data is actually the address) CLE must be low at this time, so you don't need to worry about it.

2 Therefore, when ALE is low, most of the other pins are shaded gray, which means we do not need to care about the levels of these pins during this period.

3 Similarly, the rising edge of WE has a long vertical line running through other signal lines, which also represents that the data (actually the address here) is latched on the rising edge.

Then the rest is easy to understand.

We don't need to care about tCLS because CLE is invalid at all.

tCS is the time when the CE chip select signal is valid before the rising edge of WE, that is, before the address is latched, which is the CE setup time.

What about tWC? Don't know? Don't know. Look in the manual. As mentioned before, these time numbers are given in the manual.

From the explanation in the manual above, we can see that it refers to the time of a write cycle

tWP write pulse width (that is, WE is low level limited, twp refers to the low level duration, that is, the effective time)

tWH is easy to understand, it is the high level time

ALS is the address signal ALE setup time.

ALH ALE signal effective hold time

TDS TDH Data setup and hold time

Just like the analysis of command timing above, the setup and hold time of the signal here are based on the data latch demarcation point (WE rising edge)

I believe that people who read carefully should have a general idea of ​​how to read a timing diagram after seeing this, but what we are involved in here are nothing more than the setup/hold times above.

It's a bit more complicated.

Let's take a look at a more complicated timing diagram. It's not complicated at all. It mainly explains how to know what time txx refers to without reading the manual.

This timing is not complicated, but it is not just about setup time and hold time as analyzed above. There are more time labels involved here.

But as I said before. Read the manual! The manual has a description of each time parameter. But beginners usually don’t know what these time parameters mean even if they read the manual.

Before we look at the manual, let's analyze it ourselves. Once you know the method, the manual becomes something to verify whether you are right, not something for you to find the answer.

The parameter TRC is a bit simple. Its range is the time of one RE cycle, so it should be the same as the previous tWC. It should represent the cycle time of the RE signal (one cycle of the read signal).

What about TREA? The label does not tell us much, so let's look at its start and end time. From the timing diagram, we can see that this refers to the time from RE being valid (going low) to the appearance of data.

Then tREA is the time between when the read signal is valid and when the data is read.