Software simulation to implement the iic protocol (51 as an example)

1. Overview of I2C Serial Bus

1. The I2C bus is a serial bus launched by PHLIPS. It is a high-performance serial bus with bus arbitration and high-speed and low-speed device synchronization functions required by multi-host systems.

The I2C bus has only two bidirectional signal lines, one is the data line SDA, and the other is the clock line SCL.

2. The I2C bus is connected to the positive power supply through a pull-up resistor. When the bus is idle, both lines are high. The low level output by any device connected to the bus will make the bus signal low, that is, the SDA and SCL of each device are in a line "AND" relationship.

3. Each device connected to the I2C bus has a unique address. Data transmission between the host and other devices can be done by the host sending data to other devices. In this case, the host is the transmitter. The device receiving data on the bus is the receiver. In a multi-host system, several hosts may attempt to start the bus to transmit data at the same time. In order to avoid confusion, the I2C bus must go through bus arbitration to determine which host controls the bus.

In the serial bus expansion of the 80C51 single-chip microcomputer application system, we often encounter a single-host situation with the 80C51 single-chip microcomputer as the host and other interface devices as slaves.

2. Data transmission of I2C bus

1. Data bit validity regulations

When the I2C bus is transmitting data, the data on the data line must remain stable while the clock signal is at a high level. The high or low level state of the data line is allowed to change only when the signal on the clock line is at a low level.

2. Start and stop signals

(1) When the SCL line is at a high level, the change of the SDA line from a high level to a low level indicates a start signal; when the SCL line is at a high level, the change of the SDA line from a low level to a high level indicates a stop signal.

(2) Both the start and stop signals are sent by the host. After the start signal is generated, the bus is in an occupied state; after the stop signal is generated, the bus is in an idle state.

(3) If the device connected to the I2C bus has a hardware interface for the I2C bus, it can easily detect the start and end signals.

(4) After receiving a complete data byte, the receiving device may need to complete some other tasks, such as processing internal interrupt services, and may not be able to receive the next byte immediately. At this time, the receiving device can pull the SCL line to a low level, thereby putting the host in a waiting state. When the receiving device is ready to receive the next byte, the SCL line is released to a high level, so that data transmission can continue.

3. Data transmission format

1. Byte transmission and response

Each byte must be 8 bits long. When data is transmitted, the most significant bit (MSB) is transmitted first, and each transmitted byte must be followed by an acknowledge bit (i.e., a frame has a total of 9 bits).

(1) When the slave does not respond to the host addressing signal for some reason (for example, the slave is performing real-time processing and cannot receive data on the bus), it must set the data line to a high level, and the host generates a termination signal to end the data transmission on the bus.

(2) If the slave responds to the host but cannot receive more data after a period of data transmission, the slave can notify the host by "non-response" to the first data byte that cannot be received. The host should then send a termination signal to end the continued data transmission.

(3) When the master receives data, it must send a signal to the slave to end the transmission after receiving the last data byte. This signal is implemented by a "non-response" to the slave. The slave then releases the SDA line to allow the master to generate a termination signal.

2. Data frame format

The data signals transmitted on the I2C bus are broad in nature, including both address signals and actual data signals.

After the start signal, a slave address (7 bits) must be transmitted. The 8th bit is the data transmission direction bit (R/T). "0" indicates that the host sends data (T), and "1" indicates that the host receives data (R). Each data transmission is always terminated by the termination signal generated by the host. However, if the host wants to continue to occupy the bus for new data transmission, it can not generate a termination signal and immediately send a start signal again to address another slave.

During a data transmission process on the bus, there can be the following combinations:

(1) The host sends data to the slave, and the data transmission direction remains unchanged during the entire transmission process:

Note: The shaded area indicates that data is transmitted from the host to the slave, and the unshaded area indicates that data is transmitted from the slave to the host.

A means answer, A means no answer (high level). S means start signal, P means end signal.

(2) The host reads data from the slave immediately after the first byte

(3) During the transmission process, when the transmission direction needs to be changed, the start signal and the slave address are generated once, but the read/write direction bits are exactly inverted.

4. Bus addressing

The I2C bus protocol has clear provisions: use a 7-bit addressing byte (the addressing byte is the first byte after the start signal).

1. Bit definition of addressing byte

D7 to D1 constitute the slave address. D0 is the data transfer direction bit. When it is "0", it means the host writes data to the slave, and when it is "1", it means the host reads data from the slave.

2. When the host sends the address, each slave on the bus compares the 7-bit address code with its own address. If they are the same, it believes that it is being addressed by the host and identifies itself as a transmitter or receiver based on the R/T bit.

3. The address of the slave consists of a fixed part and a programmable part. In a system, you may want to connect multiple identical slaves. The programmable part of the slave address determines the maximum number of devices of this type that can be connected to the bus. For example, if 4 of the 7 addressing bits of a slave are fixed bits and 3 are programmable bits, then only 8 identical devices can be addressed, that is, 8 identical devices can be connected to the I2C bus system.

5. Interface of 80C51 MCU I2C serial bus device

The host can use a single-chip microcomputer without an I2C bus interface, such as 80C51, AT89C2051 and other single-chip microcomputers, and use software to realize data transmission of the I2C bus, that is, signal simulation combining software and hardware.

1. Typical signal simulation

In order to ensure the reliability of data transmission, the data transmission of the standard I2C bus has strict timing requirements. The analog timing of the start signal, stop signal, sending "0" and sending "1" of the I2C bus is:

2. Typical signal simulation subroutine

1 //（1）Start signal

2 void I2CStart(void)

3 {

4     SDA = 1;

5 SomeNop() ; // greater than 4.7us

6 SCL = 1; // If sda changes from high to low during scl high level, a start signal is generated

7 SomeNop( );

8 SDA = 0; // sda：1->0

9 SomeNop() ; // greater than 4us

10 }

11 //(2) Termination signal

12 void I2cStop(void)

13 {

14     SDA = 0;

15 SomeNop() ; // greater than 4us

16 SCL = 1; // If sda changes from low to high during the scl high level period, a termination signal is generated

17 SomeNop( );

18 SDA = 1; // sda：0->1

19 SomeNop() ; // greater than 4.7us

20

21 }

22 //(3) Response signal

23 void ack()

24 {

25 flying i;

26 scl=1; // The 9th clock cycle starts at a high level

27     delay();

28 while((sda==1)&&(i<250))i++; // During the 9th clock cycle clk is at a high level, if sda is pulled low by the slave, a response signal is generated. If it times out, it is a non-response signal

29 scl=0; // The 9th clock cycle ends at a low level

30     delay();

31 }

32 //(4) Write one byte of data

33 /*

34 void write_byte(uchar dat)

35 {

36 flying i,temp;

37 temp=that;

38     for(i=0;i<8;i++)

39     {

40         temp=temp<<1;

41 scl=0; // Write 1 bit of data when scl is low

42         delay();

43 sda=CY;

44         delay();

45 scl=1; // When scl is high, the data remains stable

46         delay();

47     }

48     scl=0;

49     delay();

50 sda=1; //After writing one byte of data, release the sda ​​bus

51     delay();

52 }

53 */

54 void delay(){ ;; }

55 void write_byte(uchar dat)

56 {

57 flying i,temp;

58 temp=that;

59     for(i=0;i<8;i++)

60     {

61 scl=0; // Write 1 bit of data when scl is low

62         delay();

63 if (0x80&temp) // 1000 0000 is true, write 1; 0000 0000 is false, write 0

64         {

65             sda = 1;

66         }

67         else

68         {

69             sda = 0;

70         }

71         delay();

72 scl=1; // When scl is high, the data remains stable

73         delay();

74         temp=temp<<1;

75     }

76     scl=0;

77     delay();

78 sda=1; // Release the data bus and wait for the response (no response can be detected without releasing the data bus)

79     delay();

80 }

81 //（5）Read one byte of data

82 uchar read_byte()

83 {

84 fly i,k;

85 scl=0; // When scl is low, you can pull sda high to release the bus

86     delay();

87     sda=1;

88     delay();

89     for(i=0;i<8;i++)

90     {

91 scl=1; // When scl is high, sda is valid data

92         delay();

93 k=(k<<1)|sda; // Put 1 bit of data into k