CC2530 internal storage structure diagram

　　CPU and memory

　　The 8051 CPU core used in the CC253x chip series is a single-cycle 8051-compatible core. It has three different memory access buses (SFR, DATA and CODE/XDATA), single cycle access to SFR, DATA and main SRAM. It also includes a debug interface and an 18-input extended interrupt unit.

　　The interrupt controller provides a total of 18 interrupt sources, divided into six interrupt groups, each associated with one of four interrupt priority levels. When the device returns from active mode to idle mode, any interrupt service request is triggered. Some interrupts can also wake the device from sleep mode (power mode 1-3).

　　The memory arbiter is at the center of the system because it connects the CPU and DMA controller to physical memory and all peripherals through the SFR bus. The memory arbiter has four memory access points, and each access can be mapped to one of three physical memories: an 8-KB SRAM, flash memory, and XREG/SFR registers. It is responsible for performing arbitration and determining the order between simultaneous accesses to the same physical memory.

　　8-KB SRAM is mapped to DATA storage space and part of XDATA storage space. The 8-KB SRAM is an ultra-low-power SRAM that retains its contents even when the digital section is powered down (power modes 2 and 3). This is an important feature for low power applications.

　　A 32/64/128/256 KB flash block provides the device with in-circuit programmable non-volatile program memory, mapped to the XDATA memory space. In addition to saving program code and constants, non-volatile memory allows applications to save data that must be retained so that it can be used after the device is restarted. Using this feature, you can, for example, use saved network-specific data without having to go through the full boot, network discovery and joining process.

　　Clock and power management

　　The digital core and peripherals are powered by a 1.8-V low-dropout regulator. It provides power management features that enable low-power operation for long battery life using different power supply modes. There are five different reset sources to reset the device.

　　peripherals

　　The CC2530 includes many different peripherals, allowing application designers to develop advanced applications.

　　The debug interface implements a proprietary two-wire serial interface for in-circuit debugging. Through this debug interface, you can perform an erase of the entire flash memory, control which oscillator is enabled, stop and start user program execution, execute instructions provided by the 8051 core, set code breakpoints, and single-step debugging of all instructions in the core. Using these techniques, debugging of internal circuits and programming of external flash memory can be well performed.

　　The device contains flash memory to store program code. The flash memory is programmable through user software and debug interface. The flash controller handles writing and erasing the embedded flash memory. The flash memory controller allows page erase and 4-byte programming.

　　The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral modules control certain pins or whether they are controlled by software, and if so, whether each pin is configured as an input or output, and whether a pull-up or pull-down resistor in the pad is connected. CPU interrupts can be enabled individually on each pin. Each peripheral connected to an I/O pin can choose between two different I/O pin locations to ensure flexibility in different applications.

　　The system can use a versatile five-channel DMA controller that accesses memory using the XDATA memory space, thus being able to access all physical memory. Each channel (trigger, priority, transfer mode, addressing mode, source and destination pointers, and transfer count) is configured anywhere in memory using a DMA descriptor. Many hardware peripherals (AES core, flash controller, USART, timers, ADC interface) achieve efficient operation by using a DMA controller to transfer data between SFR or XREG addresses and Flash/SRAM. Timer 1 is a 16-bit timer with timer/PWM functionality. It has a programmable divider, a 16-bit period value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each counter/capture channel can be used as a PWM output or to capture the timing of input signal edges. It can also be configured in IR generation mode, counting Timer 3 cycles, and the output is ANDed. The output of Timer 3 is used to generate a modulated consumer IR signal with minimal CPU interaction.

　　The MAC timer (Timer 2) is specifically designed to support IEEE 802.15.4 MAC or other time slot protocols in software. The timer has a configurable timer period and an 8-bit overflow counter that can be used to keep track of the number of elapsed periods. A 16-bit capture register is also used to record the precise time when a frame start delimiter is received/transmitted, or the precise time when the transmission ends. There is also a 16-bit output compare register that can generate different strobe commands at specific times (Start RX , start TX, etc.) to the wireless module. Timer 3 and Timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable divider with an 8-bit period value and a programmable counter channel with an 8-bit compare value. Each counter channel can be used as a PWM output.

　　The sleep timer is an ultra-low power timer that counts the period of a 32-kHz crystal or 32-kHz RC oscillator. The sleep timer runs continuously in all operating modes except Power Mode 3. Typical applications for this timer are as a real-time counter, or as a wake-up timer to exit power mode 1 or 2.

　　The ADC supports 7 to 12-bit resolution at 30 kHz or 4 kHz bandwidth respectively. DC and audio conversion can use up to eight input channels (port 0). Inputs can be selected as single-ended or differential. The reference voltage can be an internal voltage, AVDD, or a single-ended or differential external signal. The ADC also has a temperature sensing input channel. ADCs can automate procedures that periodically sample or convert a sequence of channels.

　　The random number generator uses a 16-bit LFSR to generate pseudo-random numbers, which can be read by the CPU or used directly by the strobe command processor. For example, random numbers can be used to generate random keys for security.

　　The AES encryption/decryption core allows users to encrypt and decrypt data using the AES algorithm with a 128-bit key. This core is capable of supporting AES operations required by IEEE 802.15.4 MAC security, ZigBee network layer and application layer.

　　A built-in watchdog allows the CC2530 to reset itself in the event of a firmware hang. When the watchdog timer is enabled by software, it must be cleared periodically; otherwise, it resets the device when it times out. Or it can be configured for use as a general-purpose 32-kHz timer.

　　USART 0 and USART 1 are each configured as an SPI master/slave or a UART. They provide double buffering for RX and TX, as well as hardware flow control, making them ideal for high-throughput full-duplex applications. Each has its own high-precision baud rate generator, thus freeing up regular timers for other uses.

　　wireless device
 

　　CC2530 internal storage structure

　　The CC2530 features an IEEE 802.15.4 compliant wireless transceiver. The RF core controls the analog wireless module. In addition, it provides an interface between the MCU and the wireless device, which makes it possible to issue commands, read status, automate operations and determine the sequence of wireless device events. The wireless device also includes a packet filtering and address identification module.

　　There are four storage spaces in CC2530 (the structurally divided storage spaces are not actual memories, but a theoretical concept)

　　1. The CODE program memory is used to store program code and some constants. It has 16 address buses, so the addressing range of CODE is 0000H~FFFFH, a total of 64KB.

　　2. The DATA data memory is used to store data during program running. It has 8 address buses, so the addressing space of DATA is 00H~FFH, a total of 256 bytes. The lower 128 bits can be directly addressed, and the upper 128 bits can only be addressed indirectly. .

　　3. XDATA external data memory (only indirect addressing, relatively slow access speed) DMA is addressed on XDATA. This is very important. There are 16 address buses, so the addressing space of XDATA is 0000H ~ FFFFH, a total of 64K

　　4. The SFR special function register is where T1CTL, EA, P0 and other configuration registers are stored, totaling 128K. Because CC2530 has many configuration registers, some redundant registers are placed in XREG. The size of XREG is 1K XREG is accessed slower than SFR.

CC2530 internal storage structure diagram

　　The above 4 storage spaces are just concepts of 4 different addressing methods and do not represent specific physical storage devices. For example, FLASH or EEPROM can be mapped to CODE as a physical storage medium, and DRAM or SRAM can be mapped to DATA as a storage medium. CODE and DATA are concepts of storage space, and FLASH, SRAM, EEPROM, etc. are specific physical storage devices. Do not confuse these two concepts.

　　This is like a computer requiring RAM and ROM. The ROM can be a Western Digital hard drive, a Samsung hard drive, or a solid-state drive made of different materials. One is storage space, and the other is a specific physical storage device.