1. Conditions for CPU to access the chip

　　The CPU reads data from external devices by accessing the storage controller.

　　If the CPU wants to access a chip, it needs the following conditions (configuration information):

• 
  

• address line

• Data line: 8-bit/16-bit/32-bit data width

• Clock frequency　

• Other chip-related features: such as SDRAM, including row address, column address and bank

　　The principle of SDRAM access is the same as that of table retrieval. First specify a row (Row), and then specify a column (Columu), and you can accurately find the required cell. This cell is called a storage unit, and this table (storage array) is a logical Bank (Logical Bank, or L-Bank). SDRAM generally contains 4 L-banks.　　

　　Only after configuring the storage manager can you know how to access external devices.

2. Storage controller accesses SDRAM

　　2.1 Schematic diagram

　　CPU side:

　　You can look at the functions of these pins and check the SDRAM chip manual.

　　LADDR: address interface

　　LnWBE[0:3]: bank operation mode

　　LDATA: data interface

　　LnWE

　　See the data sheet for more information.

3. Configuration of storage manager　　

• bit width

• Row and column address

• refresh cycle

　　Detailed registers can be viewed at DATASHEET.

4. 2440 startup method

4.1 NAND FALSH startup

4.2 NOR FLASH

5. Code

 　　Memory controller initialization code:

　　Here we are booting from nor flash, so the parameter defined by CONFIG_SYS_TEXT_BASE is 0x0.

　　lowlevel_init.S (boardsamsungjz2440) 

  1 #define BWSCON    0x48000000

  2 

  3 /* BWSCON */

  4 #define DW8            (0x0)

  5 #define DW16            (0x1)

  6 #define DW32            (0x2)

  7 #define WAIT            (0x1<<2)

  8 #define UBLB            (0x1<<3)

  9 

 10 #define B1_BWSCON        (DW32)

 11 #define B2_BWSCON        (DW16)

 12 #define B3_BWSCON        (DW16 + WAIT + UBLB)

 13 #define B4_BWSCON (DW16)

 14 #define B5_BWSCON        (DW16)

 15 #define B6_BWSCON        (DW32)

 16 #define B7_BWSCON        (DW32)

 17 

 18 /* BANK0CON */

 19 #define B0_Tacs            0x0    /*  0clk */

 20 #define B0_Tcos            0x0    /*  0clk */

 21 #define B0_Tacc 0x7 /* 14clk */

 22 #define B0_Tcoh            0x0    /*  0clk */

 23 #define B0_Tah            0x0    /*  0clk */

 24 #define B0_Tacp            0x0

 25 #define B0_PMC            0x0    /* normal */

 26 

 27 /* BANK1CON */

 28 #define B1_Tacs            0x0    /*  0clk */

 29 #define B1_Tcos            0x0    /*  0clk */

 30 #define B1_Tacc 0x7 /* 14clk */

 31 #define B1_Tcoh            0x0    /*  0clk */

 32 #define B1_Tah            0x0    /*  0clk */

 33 #define B1_Tacp            0x0

 34 #define B1_PMC            0x0

 35 

 36 #define B2_Tacs            0x0

 37 #define B2_Tcos            0x0

 38 #define B2_Tacc 0x7

 39 #define B2_Tcoh            0x0

 40 #define B2_Tah 0x0

 41 #define B2_Tacp            0x0

 42 #define B2_PMC            0x0

 43 

 44 #define B3_Tacs            0x0    /*  0clk */

 45 #define B3_Tcos            0x3    /*  4clk */

 46 #define B3_Tacc 0x7 /* 14clk */

 47 #define B3_Tcoh            0x1    /*  1clk */

 48 #define B3_Tah 0x0 /* ​​0clk */

 49 #define B3_Tacp 0x3 /* 6clk */

 50 #define B3_PMC            0x0    /* normal */

 51 

 52 #define B4_Tacs            0x0    /*  0clk */

 53 #define B4_Tcos            0x0    /*  0clk */

 54 #define B4_Tacc            0x7    /* 14clk */

 55 #define B4_Tcoh            0x0    /*  0clk */

 56 #define B4_Tah 0x0 /* ​​0clk */

 57 #define B4_Tacp            0x0

 58 #define B4_PMC            0x0    /* normal */

 59 

 60 #define B5_Tacs            0x0    /*  0clk */

 61 #define B5_Tcos            0x0    /*  0clk */

 62 #define B5_Tacc 0x7 /* 14clk */

 63 #define B5_Tcoh            0x0    /*  0clk */

 64 #define B5_Tah            0x0    /*  0clk */

 65 #define B5_Tacp            0x0

 66 #define B5_PMC            0x0    /* normal */

 67 

 68 #define B6_MT 0x3 /* SDRAM */

 69 #define B6_Trcd 0x1

 70 #define B6_SCAN            0x1    /* 9bit */

 71 

 72 #define B7_MT 0x3 /* SDRAM */

 73 #define B7_Trcd            0x1    /* 3clk */

 74 #define B7_SCAN            0x1    /* 9bit */

 75 

 76 /* REFRESH parameter */

 77 #define REFEN 0x1 /* Refresh enable */

 78 #define TREFMD            0x0    /* CBR(CAS before RAS)/Auto refresh */

 79 #define Trp            0x0    /* 2clk */

 80 #define Trc            0x3    /* 7clk */

 81 #define Tchr            0x2    /* 3clk */

 82 #define REFCNT            1113    /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */

 83 /**************************************/

 84 

 85 .globl lowlevel_init

 86 lowlevel_init:

 87     /* memory control configuration */

 88     /* make r0 relative the current location so that it */

 89     /* reads SMRDATA out of FLASH rather than memory ! */

 90 /* Initialize memory*/

 91 ldr r0, =SMRDATA /* Place the first address (first .long) memory unit data of SMRDATA into the r0 register r0=eac */

 92     ldr    r1, =CONFIG_SYS_TEXT_BASE    /* CONFIG_SYS_TEXT_BASE=0x0(include/configs/jz2440中定义) 

 93 Base address of code*/

 94     sub    r0, r0, r1                    /* r0 = r0 -r1 */

 95 ldr r1, =BWSCON /* Bus Width Status Controller,BWSCON=0x48000000, defined in this file*/

 96 add r2, r0, #13*4 /* Assign the SMRDATA address to r2*/

 97 0:

 98 ldr r3, [r0], #4 /* Put the memory unit represented by the value of r0 into r3, and then the value of r0 is offset by 4 bits*/

 99 str r3, [r1], #4 /* Put the value of r3 into the address represented by the value of r1, and the address represented by the value of r1 is offset by 4 bits*/

100 cmp r2, r0 /* Compare r2 and r0, if not equal, execute the next sentence*/

101 bne 0b /* Jump backward to label 0*/

102 

103     /* everything is fine now */

104 mov pc, lr /* return*/

105 

106 .ltorg

107 /* the literal pools origin */

108 

109 /* 

110 * Initialize the storage controller. After this initialization, the memory can be used

111  */

112 /* The address is 0x00000eb0 */

113 SMRDATA:

114         .long 0x22011110     //BWSCON

115 .long 0x00000700 //BANKCON0

116 .long 0x00000700 //BANKCON1

117         .long 0x00000700     //BANKCON2

118         .long 0x00000700     //BANKCON3  

119 .long 0x00000740 //BANKCON4

120         .long 0x00000700     //BANKCON5

121         .long 0x00018005     //BANKCON6

122         .long 0x00018005     //BANKCON7

123         .long 0x008C04F4     //REFRESH

124 .long 0x000000B1 //BANKSIZE

125         .long 0x00000030     //MRSRB6

126         .long 0x00000030     //MRSRB7