LPC824-pin configuration IOCON

From the previous example, we know that the input/output port (i.e. I/O port) is the only channel that LPC824 can rely on for control. If the CPU core of the chip is compared to the human brain, then the I/O port of the chip is equivalent to For human facial features and limbs, it is responsible for the acquisition of information and the execution of actions. If the chip does not have an I/O port, the CPU itself will become meaningless, so it is necessary to understand their internal structure and its detailed configuration. The internal structure of the LPC824 standard I/O pins is shown in the figure below.

In the internal structure diagram, PIN is a bit in the input/output port, which is a pin of GPIO. The ESD connected to it is an electrostatic resistor, which is used to release electrostatic interference on the pin. The logic gates and MOS tubes in the upper part are used to control the digital output. The MOS tubes are controlled by three signals: open-drain enable, output enable and CPU output, which are used to determine the strong pull-up, strong pull-down and output level. The logic gates and MOS tubes in the middle part are used to control the relay mode. When the relay is enabled, when the pin is at a high level, the relay mode will enable the pull-up resistor, and when the pin is at a low level, the pull-up resistor will be enabled. Pull-down resistor. This causes the pin to maintain its last known state when configured as an input and not driven externally. If the pin is not driven temporarily, relay mode is often used to prevent the pin from floating (because the pin can consume a lot of power when it is in an indeterminate state). The logic gates in the lower half are used to shape and read the level status on the pin, and can also control whether the input level is inverted. At the bottom of the picture is the analog input of the control pin, which is used to read analog signals. 

In LPC824, each pin can be configured with the following electrical properties:
1. Configurable pull-up/pull-down resistor
2. Programmable open-drain mode
3. Hysteresis mode
4. Input inverter
5. Glitch digital filter with programmable time Constant
6. Simulation mode

Among them, pins PIO0_10 and PIO0_11 are also true open-drain pins and can be configured for different I2C bus speeds.

In LPC824, each port pin PIO0_x is assigned an IOCON register to control the function and electrical characteristics of the pin. The following table lists the IOCON registers and their offset addresses used by all 29 pins.

In the MDK environment, for the above 29 IOCON registers, the following structure is defined to describe the type of IOCON register group.

typedef struct {
__IO uint32_t PIO0_17;
__IO uint32_t PIO0_13;
__IO uint32_t PIO0_12;
__IO uint32_t PIO0_5; __IO uint32_t PIO0_4;
__IO uint32_t PIO0_3;
__IO uint32_t PIO0_2
;
__IO uint32_t P IO0_11;
__IO uint32_t PIO0_10;
__IO uint32_t PIO0_16;
__IO uint32_t PIO0_15;
__IO uint32_t PIO0_1 ;
__I uint32_t RESERVED0; __IO uint32_t PIO0_8;
__IO uint32_t PIO0_7; __IO uint32_t PIO0_6; __IO uint32_t PIO0_0; __IO uint32_t PIO0_14; __I uint32_t RESERVED1 ; __IO uint32_t PIO0_28 ; __IO uint32_t PIO0_27; __IO uint32_t PIO0_26; __IO uint32_t PIO0_25; __IO uint32_t PIO0_24; __IO uint32_t PIO0_23; __IO uint32_t PIO0_22; __IO uint32_t PIO0_21; __IO uint32_t PIO0_20; __IO uint32_t PIO0_19; __IO uint32_t PIO0_18; } LPC_IOCON_Type;

As discussed in the previous GPIO discussion, the base address of the IOCON register group is 0x40044000. To force the base address pointer to the above structure, the following definition must be added.

#define LPC_IOCON_BASE 0x40044000UL
#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)

In this way, you can use the form "LPC_IOCON->PIO0_x" to reference the IOCON register of a certain pin.  Since there are as many as 29 IOCON registers, and the structure of each one is basically the same, two examples will be discussed below, and the others can be used as a reference.

Given below is the entire bit structure of the PIO0_17 pin configuration register, whose byte address is 0x40044000.

(1) Bits 0~2 are reserved bits.
(2) The third and fourth bits (MODE) are used to select the function mode. The values ​​from 0x0 to 0x3 correspond to the selection of four modes: invalid, pull-up, pull-down and relay respectively. The default is pull-up.
(3) Bit 5 (HYS) is used to select whether the pin uses hysteresis. It is disabled when set to 0 and enabled when set to 1. The default is disabled.
(4) Bit 6 (INV) is used to select whether the pin is reversed when inputting. When it is set to 0, it is not reversed. When it is set to 1, it is reversed. The default is not reversed.
(5) Bits 7~9 are reserved bits.
(6) Bit 10 (OD) is used to select whether the pin is open drain. It is disabled when set to 0 and enabled when set to 1. The default is disabled. Note: The open drain here is not a true open drain mode.
(7) The 11th and 12th bits (S_MODE) are used to select the digital filter sampling mode. The values ​​from 0x0 to 0x3 correspond to selecting bypass, 1, 2, and 3 clock cycles respectively. The default is bypass.
(8) Bits 13~15 (CLK_DIV) are used to select the frequency division of the peripheral clock. This clock is used to input the filter sampling clock. The values ​​from 0x0 to 0x6 respectively select the frequency division of 0~6. The default is no frequency division.
(9) Bits 16~31 are reserved bits. 

Although only the configuration register of the PIO0_17 pin is given above, the rest of the pin configuration registers are basically the same, so I will not list them one by one. But there are two registers that are slightly different. They are the two pin configuration registers PIO0_10 and PIO0_11. The following is the full bit structure of the PIO0_10 pin configuration register.

(1) Bits 0~5 are reserved bits.
(2) Bit 6 (INV) is used to select whether the pin is reversed when inputting. When it is set to 0, it is not reversed. When it is set to 1, it is reversed. The default is not reversed.
(3) Bit 7 is a reserved bit.
(4) The 8th and 9th bits (I2CMODE) are used to select the pin I2C mode. The values ​​from 0x0 to 0x3 correspond to the selection of standard/fast I2C mode, standard GPIO function mode (requires external pull-up), ultra-fast I2C mode, Reserved, defaults to standard/fast I2C mode.
(5) The 10th bit is a reserved bit.
(6) The 11th and 12th bits (S_MODE) are used to select the digital filter sampling mode. The values ​​from 0x0 to 0x3 correspond to selecting bypass, 1, 2, and 3 clock cycles respectively. The default is bypass.
(7) Bits 13~15 (CLK_DIV) are used to select the frequency division of the peripheral clock. This clock is used to input the filter sampling clock. The values ​​from 0x0 to 0x6 respectively select the frequency division of 0~6. The default is no frequency division.
(8) Bits 16~31 are reserved bits.

It can be seen that since the two pins GPIO0_10 and GPIO0_11 are used to connect I2C devices by default, they are all true open-drain structures, so there is no need for pull-down selection and open-drain selection. However, when actually connecting an I2C device, an external pull-up resistor must be connected to the two pins.  This will be discussed in detail in the I2C module section.

At this point, we can summarize the default pin status of LPC824. PIO0_2, PIO0_3 and PIO0_5 are non-GPIO pins, GPIO0_10 and GPIO0_11 are true open-drain I2C standard/fast pins, and other pins are GPIO pins. Pin, status is digital mode, input direction, pull-up enabled, hysteresis disabled. Another point to note when configuring the IOCON register is that the reserved bit with a reset value of 1 in the IOCON register must be written with 1. In addition, the IOCON clock (located in bit 18 in the SYSAHBCLKCTRL register) must be turned on before configuring IOCON, otherwise the configuration cannot be performed. After the configuration is completed, the clock must be turned off to save power.

The external crystal oscillator function used in the first example above is configured like this. Let’s review it again:

void Ext_osc(void)
{
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); //Enable IOCON clock
LPC_IOCON->PIO0_8 &= ~(3 << 3); //Configure the P0_8 pin without pull-down Resistor mode
LPC_IOCON->PIO0_9 &= ~(3 << 3); //Configure the P0_9 pin as a pull-down resistor mode
LPC_SWM->PINENABLE0 &= ~(3 << 6); //Put P0_8 and P0_9 The pin configuration is XTALIN, XTALOUT pin
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18); //Disable IOCON clock
}

Through the previous discussion, the content of this function should be fully understood.