The common JTAG cable structure is relatively simple. One end is DB25, which is connected to the parallel port of the computer. In the middle, it passes through 74HC244 and some resistors to achieve level conversion (5V3.3V?) (there are also more cumbersome ones that only use a few 100 Ohm resistors. Solution), the JTAG header at the other end is connected to the JTAG interface of the target board.
The parallel port DB25 was originally mainly used to connect printers. Its pin definition is as follows:
25 Pin D-Sub SPP SIGNAL DIRECTION IN/OUT
1 /Strobe In/Out
2 Data 0 Out
3 Data 1 Out
4 Data 2 Out
5 Data 3 Out
6 Data 4 Out
7 Data 5 Out
8 Data 6 Out
9 Data 7 Out
10 /ACK In
11 Busy In
12 Paper Out In
13 Select In
14 /Line Feed In/Out
15 /Error In
16 /INIT In/Out
17 /Select In In/Out
18-25 Ground GND
is visible, the data lines Pin2~Pin9 can be used to send data, and Pin10~Pin13 can be used to receive data.
The data transmission form of JTAG is serial, mainly using the following pins:
TDI (Test Data In)
TDO (Test Data Out)
TCK (Test ClocK)
TMS (Test Mode Select)
TRST (Test ReSeT) optional.
Therefore, DB25- JTAG actually only utilizes a few of the DB25's wires. However, since all 8 data lines of DB25 can be used as output, various JTAG lines using different Pin Assignment have appeared on the market.
For example, Wiggler's Pin assignment:
TMS : Pin3 (D1)
TCK : Pin4 (D2)
TDI : Pin5 (D3)
TDO : Pin11 (Busy)
SRST : Pin2 (D0)
TRST : Pin6 (D4)
(See Wiggler's circuit diagram, but in the end nSRST and nTRST may not necessarily be used, and the definitions in H-JTAG are also different. TRST is Pin2 and there is no SRST.)
There is another connection method in H-JTAG - STD, which is defined as follows:
TMS: Pin3 (D1)
TCK: Pin2 (D0)
TDI: Pin8 (D6)
TDO: Pin13 (Select)
SRST: N/A
TRST: Pin4 (D2)
The programming program SJF2410 of S3C2410 uses:
TCK: Pin2 (D0)
TDI : Pin3 (D1)
TMS : Pin4 (D2)
TDO : Pin11 (Busy)
This can be seen in the jtag.h file in the source code.
In addition to the various Pin Assignment solutions for DB25, the JTAG connector also has several standards such as 20pin, 14pin, 12pin, and 10pin. The DB25-JTAG conversion board provided with the ARM9 development board here is very interesting. There is only one 244 on it, but it has three 20pin interfaces: Wiggler, STD, and S3C2410. Since the Pin Assignment of the 20pin connector is fixed and the three interfaces correspond to the three connection methods on the DB25 side, the development board can choose different interfaces to connect according to the programs running on the PC.
The definition of 20Pin Connector is as follows (refer to this picture):
Vcc ← 1 2 → NC
nTRST ← 3 4 → GND
TDI ←5 6 → GND
TMS ←7 8 → GND
TCK ←9 10 → GND
GND ←11 12 → GND
TDO ←13 14 → GND
NRESET ←15 16 → GND
NC ←17 18 → GND
NC ←19 20 → GND
14Pin:
nTRST ← 1 2 → GND
TDI ← 3 4 → GND
TDO ← 5 6 → GND
TMS ←7 8 → GND
TCK ←9 10 → GND
nSRST ←11 12 → n/a
DINT ←13 14 → Vcc
(DINT pin is used to raise Debug Interrupt. Many chips has no this pin.)
12Pin:
nTRST ← 1 2 → GND
TDI ← 3 4 → GND
TDO ← 5 6 → GND
TMS ← 7 8 → GND
TCK ← 9 10 → GND
nSRST ←11 12 → GND
10Pin:
TCK ← 1 2 → Vcc
TDI ← 3 4 → Vcc
TDO ← 5 6 → GND
TMS ← 7 8 → GND
nTRST ← 9 10 → GND
Regarding several JTAG signals, a document is provided on the H-JTAG homepage, which introduces this:
…Next, let’s start with TAP (Test Access Port).
TAP is a general port through which all data registers (DR) and instruction registers (IR) provided by the chip can be accessed. The control of the entire TAP is completed through the TAP Controller. TAP includes a total of 5 signal interfaces TCK, TMS, TDI, TDO and TRST: 4 of them are input signal interfaces and the other 1 is an output signal interface. Generally, the development boards we see have a JTAG interface, and the main signal interfaces of the JTAG interface are these five. Next, I will first introduce these 5 interface signals and their functions.
Test Clock Input (TCK)
TCK provides an independent, basic clock signal for TAP operation. All operations of TAP are driven by this clock signal. TCK is mandatory in the IEEE 1149.1 standard.
Test Mode Selection Input (TMS)
The TMS signal is used to control the transition of the TAP state machine. Through the TMS signal, TAP can be controlled to convert between different states. The TMS signal is valid on the rising edge of TCK. TMS is mandatory in the IEEE 1149.1 standard.
Test Data Input (TDI)
TDI is the interface for data input. All data to be input to a specific register is input serially bit by bit through the TDI interface (driven by TCK). TDI is mandatory in the IEEE 1149.1 standard.
Test Data Output (TDO)
TDO is the interface for data output. All data to be output from a specific register is output serially bit by bit through the TDO interface (driven by TCK). TDO is mandatory in the IEEE 1149.1 standard.
Test Reset Input (TRST)
TRST can be used to reset (initialize) the TAP Controller. However, this signal interface is optional in the IEEE 1149.1 standard and is not mandatory. Because the TAP Controller can also be reset (initialized) through TMS.
In fact, the general process of accessing the data register (DR) through the TAP interface is:
1. Select a data register to be accessed through the instruction register (IR);
2. Connect the selected data register to TDI and TDO. time;
3. Driven by TCK, the required data is input into the selected data register through TDI; at the same time, the data in the selected data register is read out through TDO.
In addition, the optional signal nSRST is defined as follows (see Reference 1):
nSRST is a "system reset" signal and acts like conventional "Reset' button.
Reference:
[1] http://www.linux-mips.org /wiki/JTAG
[2] http://en.wikipedia.org/wiki/Jtag
[3] http://docwiki.gumstix.org/JTAG
[4] http://wiki.openwrt.org/OpenWrtDocs/Customizing /Hardware/JTAG_Cable
[5] http://www.bluewaternz.com/corporate/uni/unikit/jtag/
From here we can understand why the jtag interfaces of various board companies on the market have 20pin, 10pin, 12pin, and 14pin. After reading
the documentation of master litron, http://blog.chinaunix.net/u/23070/showart.php?id=157735
changed the jtag.h file
// Pin Connections
// TCK :DATA[0] (2 ) // my is 4 DATA[2]
// TDI :DATA[1] (3) // my is 5 DATA[3]
// TMS :DATA[2] (4) //my is 3 DATA[1]
// TDO :STATUS[7] (11)
//#define TCK_H 0x01
#define TCK_H 0x04
//#define TDI_H 0x02
#define TDI_H 0x08
//#define TMS_H 0x04
#define TMS_H 0x02Compile
, program,
[root@hujunlinux Jflash]# ./Jflash-s3c2410 vivi /t=5
+------------------------------------------------ +
| SEC JTAG FLASH(SJF) v 0.11 +
| modified by MIZI 2002.7.13 +
+-------------------------------- ------+
> flashType="5"
> S3C2410X(ID=0x0032409d) is detected.
> K9S1208 is detected. ID="0xec76"
K9S1208 NAND Flash JTAG Programmer Ver 0.0
0:K9S1208 Program 1:K9S1208 Pr BlkPage 2 : Exit
Select the function to test :0
[SMC(K9S1208) NAND Flash Writing Program]
Source size: 0x13a53
Available target block number: 0~4095
Input target block number:0
target start block number =0
target size (0x4000*n) =0x14000
STATUS:Epppppppppppppppppppppppppp Epppppppppppppppppppppppppp
Epppppppppppppppppppppp
pppppppppppppppppppppp
K9S1208 NAND Flash JTAG Programmer Ver 0.0 0:K9S1208 Program 1:K9S1208 Pr BlkPage 2: Exit Select the function to test :2 jflash can be programmed, but after burning vivi into it, running minicom, there is no output from the serial port, but when using sjf2410 to program the same vivi under windows, it runs normally and encounters This problem is because after programming vivi, I did not turn off the power and then turn on the board. I just pressed the Reset button on the board, turned it off and on again, and the serial port saw the startup information of vivi. Here is my Jflash source code, indicating that it is suitable to use wiggler's jtag, // TCK :DATA[0] (2) // my is 4 DATA[2] // TDI :DATA[1] (3) // my is 5 DATA[3] // TMS :DATA[2] (4) //my is 3 DATA[1] means TCK->pin4, which is DATA[2]. Pin2-pin9 should form DATA, so pin2 It is DATA[0] and so on, TDI, TMS. The TDO uses pin11, because the TDO of my jtag and the litron hero are the same, pin11, so I don’t care about it.
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