S3C2410 pin
S3C2410 LCD controller is used to transmit video data and generate necessary control signals, such as VFRAME, VLINE, VCLK, VM, etc. In addition to control signals, S3C2410 also has a port VD[23 z O] for outputting video data, as shown in Figure 1. The pins to be used are described as follows: VCLK——pixel clock signal; VD[23:O]——LCD pixel output port; VM/VDEN/TP—LCD driver AC bias signal (STN)/data enable Signal (TFT)/SEC TFT source driver data loading pulse signal.
Figure 1 External pin diagram of S3C2410 LCD controller
The LCD controller consists of REGBANK, LCDCDMA, VIDPRCS, TIMEGEN and LPC3600 (see Figure 2).
REGBANK has 17 programmable register groups and 256×16 palette memory for setting the LCD controller. LCDCDMA is a dedicated DMA that automatically transfers video data from the frame memory to the LCD controller. With this special DMA, the video data can be displayed on the screen without CPU intervention. VIDPRCS accepts the video data from LCDCDMA and sends it to the LCD driver via VDF23:O] after changing it to the appropriate data format, such as 4/8 single scan or 4 double scan display mode. TIMEGEN consists of programmable logic to support different requirements for interface timing and speed of different LCD drivers. TIMEGEN generates VFRAME, VLINE, VCLK, VM signals, etc.
The data flow is described as follows: FIFO memory is located in LCDCDMA. When the FIFO is empty or partially empty, LCDCDMA requires data to be fetched from the frame memory based on the burst transfer mode and stored in the image data to be displayed. This frame memory is a buffer opened in RAM by the LCD controller. When this transfer request is received by the bus arbiter in the memory controller, 4 words will be successfully transferred from the system memory to the internal FIFO. The total size of FIFO is 28 words, of which the low-order FIFOL is 12 words and the high-order FIFOH is 16 words. S3C241O has two FIFOs to support dual scan display mode. In single scan mode, only one FIFO (FIFOH) is used.
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