C51 language interrupt function structure, C51 interrupt function writing method

1.1 Interrupt Enable Control The CPU's opening and masking of all interrupts and a certain interrupt source of the interrupt system are controlled by the interrupt enable register IE. EX0 (IE.0), external interrupt 0 enable bit; ET0 (IE.1), timer/counter T0 interrupt enable bit; EX1 (IE.2), external interrupt 0 enable bit; ET1 (IE.3), timer/counter T1 interrupt enable bit; ES (IE.4), serial port interrupt enable bit; EA (IE.7), CPU interrupt enable (total enable) bit. The operation of the 80C51 microcontroller timer/counter is controlled by two special function registers. TMOD is used to set its working mode; TCON is used to control its startup and interrupt application. 1. Working mode register TMOD The working mode register TMOD is used to set the working mode of the timer/counter, and the lower four bits are used.

2. T0, the upper four bits are used for T1. Its format is as follows: GATE: gate control bit. When GATE0, as long as TR0 or TR1 in TCON is set to 1 by software, the timer/counter can be started; when GATE1, TR0 or TR1 must be set to 1 by software, and the external interrupt pin INT0/1 is also at a high level, the timer/counter can be started. That is, the start condition of the timer at this time adds the condition that the INT0/1 pin is at a high level. : Timing/counting mode selection bit. C/T 0 is the timing mode; C/T=1 is the counting mode. M1M0: working mode setting bit. The timer/counter has four working modes, which are set by M1M0. The lower 4 bits of TCON are used to control external interrupts, which have been introduced above. The upper 4 bits of TCON are used to control the timer/counter.

3. Start and interrupt application. Its format is as follows: TF1 (TCON.7): T1 overflow interrupt request flag. When T1 counts overflow, TF1 is automatically set to 1 by hardware. After the CPU responds to the interrupt, TF1 is automatically cleared to 0 by hardware. When T1 is working, the CPU can query the status of TF1 at any time. Therefore, TF1 can be used as a flag for query testing. TF1 can also be set to 1 or cleared to 0 by software, which has the same effect as setting 1 or clearing 0 by hardware. TR1 (TCON.6): T1 operation control bit. When TR1 is set to 1, T1 starts working; when TR1 is set to 0, T1 stops working. TR1 is set to 1 or cleared to 0 by software. Therefore, the start and stop of the timer/counter can be controlled by software. TF0 (TCON.5): T0 overflow interrupt request flag, its function is similar to TF1. TR0 (TCO.

4. N.4): T0 operation control bit, its function is similar to TR1. 3.3.5 Example of timer/counter application The initialization program should complete the following tasks: Assign TMOD to determine the working mode of T0 and T1. Calculate the initial value and write it to TH0, TL0 or TH1, TL1. When in interrupt mode, assign IE to open the interrupt. Set TR0 or TR1 to start the timer/counter timing or counting. Initialization of timer T0 interrupt TMOD=0x01; Set the working mode to 16-bit timer TH0=(65536-50000)/256; Assign the high four values ​​of timer T0 to 50MS (modulo 256) TL0=(65536-50000)%256; Assign the low four values ​​of timer T0 to 50MS (modulo 256).

5. Remainder) EA=1; turn on general interrupt ET0=1; turn on timer T0 interrupt TR0=1; start timer T0. When the timer time is up and an interrupt is generated, it will automatically jump to the following interrupt function. The interrupt function does not need to make any declaration; void timer0() interrupt 1 The order of the 5 interrupt sources: 0 represents external interrupt 0 interrupt, 1 represents timer/counter 0 interrupt, 2 represents external interrupt 1 interrupt, 3 represents timer/counter 1, 4 represents serial interrupt interrupt TH0=(65536-50000)/256; reload initial value TL0=(65536-50000)%256; reload initial value and write down what the CPU needs to handle. Interrupt response condition The interrupt source has an interrupt request; the interrupt enable bit of this interrupt source is 1; the CPU turns on the interrupt (ie.

6. EA=1). Only when the above three conditions are met at the same time, the CPU may respond to the interrupt. P3.2 port external interrupt EA=1;/Open general interrupt EX0=1;/Open external interrupt 0/IT0=1;/When IT=0, it is the level external interrupt trigger mode, when IT=1, it is the bit jump edge external interrupt trigger mode TCON=0x01; (This is to set IT to 1 for the register, and the effect is the same as IT0=1) Because the address of TCON is divisible by 8, it can be bit operated. When the conditions of the external interrupt are met, the following interrupt function is executed void exter0() interrupt 0 The order of the 5 interrupt sources: 0 represents external interrupt 0 interrupt, 1 represents timer/counter 0 interrupt, 2 represents external interrupt 1 interrupt, 3 represents timer/.

7. Counter 1, 4 represents the interrupt of serial interrupt. Just write what the CPU wants to process here and it will be OK.""""At the end, Xiao Bian gives you a passage. Minand once said, people who learn to learn are very happy people. In every wonderful life, learning is an eternal theme. As a professional clerical and teaching position, I understand the importance of continuous 。

8、learning, life is diligent, nothing can be gained, only continuous learning can achieve better self. Only by constantly learning and mastering the latest relevant knowledge, can employees from all walks of life keep up with the pace of enterprise development and innovate to meet the needs of the market. This document is also edited by my studio professionals, there may be errors in the document, if there are errors, please correct, thank you。