80C51 single chip microcomputer learning hardware structure

Publisher:小悟空111Latest update time:2022-06-17 Source: eefocusKeywords:80C51 Reading articles on mobile phones Scan QR code
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1.80C51 MCU internal logic structure

A single-chip microcomputer is a microcomputer that integrates the CPU, storage, input and output interfaces, timer/counter and clock circuits into a single chip. It is mainly composed of the following parts.

(1) Central Processing Unit (CPU)

Including an operator and a controller.

The operation circuit is based on ALU, which completes arithmetic and logical operations. The operation results are stored in ACC, and the characteristics of the operation results are stored in PSW.

The control circuit is the command and control component of the single-chip microcomputer, ensuring that all parts of the single-chip microcomputer can work automatically and in a coordinated manner. The program counter PC is a 16-bit register. The content of PC is the address of the next instruction to be executed. It has the function of automatically adding 1 to realize the sequential execution of the program.

(2) Memory

Classification:

Random Access Memory RAM: can be read and written, and the information disappears after the computer is turned off. It can be divided into static RAM (SRAM) and dynamic RAM (DRAM).

Read-only memory: Information does not disappear after the computer is turned off.

Mask ROM: Information is written once by the manufacturer at the time of shipment.

Programmable RROM: Information is written once by the user.

Erasable Programmable EPROM: The written contents can be erased by ultraviolet light.

Electrically Erasable Programmable ROM (EEPROM): can be erased and rewritten using electrical signals.

storage capacity:

Storage capacity refers to the amount of binary information that the memory can hold. The memory capacity of an M-bit address bus and an N-bit data bus is (2^M)*N bits.

The memory of the 80C51 microcontroller includes internal RAM (128B, the upper 128B are dedicated registers), external RAM (64KB), internal ROM (4KB mask ROM), and external ROM (64KB).

(3) Input and output interface

4 8-bit parallel I/O ports (P0, P1, P2, P3)

(4) Other resources

One full-duplex serial port, five interrupt sources, two 16-bit timers/counters, and clock circuit.


2. Signal pins of 80C51 microcontroller

(1) Power supply part: VCC connects to +5V and VSS connects to ground.

(2) Clock circuit part: XTAL1 and XTAL2 are connected to the crystal oscillator.

1 machine cycle = 6 states = 12 beats

The machine cycle of a 6MHZ crystal is 2us, and the machine cycle of a 12MHZ crystal is 1us.

(3) I/O port part: P0 - 8-bit data bus/address bus lower 8 bits, P1 - user port, P2 - address high 8 bits, P3 - second function.

(4) Control part:

The address latch control signal ALE is used to control the low 8-bit address output from port P0 to be sent into the latch for latching.

External program memory read select signal PSEN is valid at low level to implement the read operation of external ROM unit.

The control signal EA for accessing the program memory only reads the external ROM when it is at a low level, and reads the internal ROM first and then the external ROM when it is at a high level.

The reset signal RST is valid when the input reset signal remains high for more than two mechanical cycles.

Reset value: PC = 0000H, SP = 07H, P0 = 0FFH


3. Basic structure and function of internal RAM

The lower 128-unit area of ​​the internal data memory of 80C51 is called internal RAM, with addresses from 00 to 7FH.

(1) Register area (00~1FH)

There are four groups, numbered 0, 1, 2, and 3. Each group has 8 registers, numbered from R7 to R0 in the group. The state combination of RS1 and RS0 bits in PSW determines which group it is in.

(2) Bit addressing area (20H~2FH)

The bit operation can be performed on each bit in the unit. There are 128 addressable bits in 16 byte units, and the bit address is 00~7FH. The starting bit address D0 = (byte address - 20H) * 8

(3) User RAM area (30H~7FH) stack, buffer

The stack is created in the internal RAM, and its biggest feature is the "last in, first out" data operation principle.

Two functions: protect breakpoint and protect context. Two operations: push and pop.

SP stack pointer, its content is the address of the top unit of the stack.


4. Special registers (internal data memory high 128 units)

(1) Accumulator A (ACC)

(2) Register B

(3) Program status word PSW

CY——Carry flag, carry or borrow of the highest bit.

AC——Half carry flag, carry or borrow from the lower 4 bits to the higher 4 bits.

OV - overflow flag. When numbers with the same sign are added, the result has different signs, which means overflow. When numbers with different signs are subtracted, the result has the same sign as the subtrahend, which means overflow.

P is the number of 1s in A. An odd number of P=1, an even number of P=0.

(4) Data pointer DPTR: The only 16-bit register in 80C51 for user use. The high eight bits are DPH and the low eight bits are DPL.

Keywords:80C51 Reference address:80C51 single chip microcomputer learning hardware structure

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