Understand ARM interrupt principles and interrupt nesting

ARM has seven modes, we are here to discuss SVC, IRQ and FIQ modes

usr (user mode), fiq (fast interrupt mode), irq (interrupt mode), svc (supervisory mode), abt (data access termination mode), sys (system mode), und (undefined instruction abort mode)

① We assume that the ARM core has two interrupt pins (actually invisible), one is called irq pin and the other is called fiq pin. In the ARM cpsr, there is an I bit and an F bit, which are used to disable IRQ and FIQ respectively.

② Let's not talk about the interrupt controller, just talk about the ARM core. Under normal circumstances, the ARM core just mechanically follows the instructions of the PC to do things. When the I and F bits in the CPSR are 1, IRQ and FIQ are all in a disabled state. No matter what kind of interrupt signal you send on the irq pin and fiq pin, ARM will not pay attention to you, and you can't interrupt it at all, because it is "deaf" and "blind".

③ When the I bit and F bit are 0, when an interrupt signal comes from the irq pin, the current work of the arm will be interrupted, and the IRQ mode will be switched to the corresponding exception vector table (vector) position to execute the code. This process is automatic, but you have to do it yourself to return to the place where the interrupt was interrupted.

④ When you jump to the exception vector table and are in IRQ mode, if an interrupt signal comes from the irq pin again, ARM will ignore you. The irq pin is like a secretary, and the ARM core is like a boss. The boss is working, and then a customer comes. The secretary interrupts and lets the customer in. If another customer comes, either the secretary keeps knocking on the door to ask, or the customer leaves. The boss will ignore you if he has not finished meeting with the first customer.

⑤ But there is an exception. When ARM is in IRQ mode, an interrupt signal comes from fiq pin. What is fiq pin? Fast interrupt, just like the police come to investigate criminal cases. They don’t care whether the boss is meeting with customers or not. They interrupt directly, enter fiq mode, and jump to the corresponding fiq exception vector table to execute code. If the police come again when ARM is processing FIQ mode, there will be no hope. They are all law enforcement officers. You can’t stop me. What if irq pin comes at this time? I will ignore it. I am investigating a case. How dare they interfere with public affairs?

Conclusion: IRQ mode can only be interrupted by FIQ mode, and no one can interrupt FIQ mode.

If the interrupt is not working, it is useless to use irq pin or fiq pin to send interrupt signal.

Except for fiq being able to interrupt irq, there is no so-called interrupt nesting.

But after all, the irq pin and fiq pin together only have 2 pins. How to deal with so many interrupt sources? It is impossible for everyone to knock on the door directly.

Next, let's talk about who sends the signal to the irq pin or fiq pin. As you can see from the above, it may be the boss, the customer, or the police. In ARM, this matter is managed by the interrupt controller.

Ⅰ. Take the simplest 2410/2440 interrupt controller as an example. The interrupt controller plus a sub-interrupt controller and an external interrupt controller manage more than 50 interrupt resources, that is, more than 50 pins. Except for the external interrupt, these pins have specified functions, such as WDT, LCD, DMA, etc. This function cannot be changed because the internal hardware connection of 2410/2440 has been determined.

Ⅱ. When both WDT and DMA interrupts come, they will be sent to the SRCPND register. Both interrupts are in it. Which one should be sent to ARM? At this time, first look at INTMOD, which is the interrupt mode register: which interrupt is set as a fast interrupt, which one will be sent up; what if both are set as fast interrupts? This is impossible, because only one interrupt can be set as a fast interrupt at the same time. Therefore, if there is a fast interrupt, at this time, send an interrupt signal directly to the fiq pin to interrupt ARM.

III. If there is no fast interrupt, then check INTMSK to see if WDT and DMA are blocked. If DMA is blocked in INTMSK, only WDT continues to send upward. If neither is blocked, then they both enter the priority register PRIORITY at the same time. Here, according to the priority setting, a high priority and a low priority will be separated. The one with a high priority is sent to the INTPND register, so INTPND has only one interrupt in it at any time. As long as there is an interrupt in INTPND, the irq pin will not keep sending interrupt signals to ARM. When it is sent for the first time, it interrupts ARM. At this time, ARM enters the corresponding exception vector and is in IRQ mode.

IV. At this time, INTPND still continuously sends interrupt signals to ARM through irq pin, but ARM is already in IRQ mode and will not respond to you. When you have finished processing the interrupt and want to exit IRQ mode, be careful. If you do not clear the interrupt bit in INTPND before exiting IRQ mode, you will be interrupted again just after exiting IRQ mode, because INTPND has been sending interrupt signals. Therefore, be sure to clear the interrupt bit in INTPND before exiting IRQ mode.

Ⅴ. It is not enough to just clear the bits in INTPND, because the WDT and DMA interrupts are in SRCPND. When you just clear INTPND, another interrupt is selected in SRCPND and sent to INTPND. So the correct way to handle it is to clear the corresponding interrupt bit in SRCPND before exiting IRQ mode, and then clear the corresponding bit in INTPND. Please note that there may be multiple bits in SRCPND, so just clear the interrupt you have handled, but there may only be one bit in INTPND, so just clear it directly.

Let's talk about Linux.

1. Linux does not use FIQ, only IRQ. But sometimes an interrupt needs to be processed for a long time. Do we need to occupy IRQ mode for that long? No, Linux simply records what interrupt it is in IRQ mode and immediately switches back to SVC mode. In other words, Linux interrupt processing is all processed in SVC mode.

2. So how does the interrupt number come from? It is fixed on ARM, and there is only one way to get the corresponding interrupt number: query irqs.h. First, register an interrupt handler with an interrupt number. When an interrupt occurs, how does Linux know that it is an interrupt with this interrupt number? When processing an interrupt, first read INTPND, and then read EINTPEND or SUBSRCPND as needed to calculate an interrupt number. The corresponding processing algorithm is in the macro get_irq_nr_base. The interrupt number in irqs.h is calculated according to this algorithm.