S3C2440A clock structure analysis (ARM9 architecture)

1. Clock Tree Analysis

S3C2440A clock tree

From the upper left corner of the above figure, we can see that S3C2440A supports two external clock source inputs. One is through the external oscillator circuit connected to XTIpll and XTOpll (generally composed of a crystal oscillator as the core), and the other is through the ready-made clock frequency input through EXTCLK.

After the clock is input into the chip, it is sent to MPLL (main phase-locked loop) and UPLL (USB phase-locked loop) for frequency multiplication. The clock signal from MPLL is called FCLK, which is generally used directly to provide the clock signal to the CPU core; the clock signal from UPLL is called UCLK, which is generally used to provide the clock signal to the USB. After FCLK is divided by HDIVN and PDIVN, it will generate HCLK and PCLK. The former is generally used to provide clock signals to AHB high-speed bus and high-speed peripherals, such as USB modules, NAND FLASH controllers, etc.; the latter is generally used for APB peripheral bus to provide signals to low-speed peripherals, such as various serial communication modules, external GPIO, etc.

The following is an excerpt from the S3C2440A data sheet describing the various clock signals:

USB host interface and USB device interface needs 48Mhz clock. In the S3C2440A, the USB dedicated PLL (UPLL) generates 48Mhz for USB. UCLK does not fed until the PLL (UPLL) is configured.

FCLK is used by ARM920T. HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB host block. PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I

《S3C2440A 32-BIT CMOS MICROCONTROLLER USER'S MANUAL》 Revision 1.3

2. Clock Tree Initialization

Before powering on the chip, you need to configure the clock source used by modifying the OM3 and OM2 pins. The relationship between the pins and the corresponding settings is shown in the following table:

Then start setting the registers! The overall setting process is: 1. Set the delay time for the phase-locked loop to take effect; 2. Set the frequency division coefficient of PCLK and HCLK; 3. Configure the CPU to enter asynchronous mode so that the CPU can use FCLK as the clock source; 4. Set UCLK and FCLK;

The first thing you need to set is the LOCK TIME COUNT REGISTER (LOCKTIME). This register is used as the delay count for the phase-locked loop to take effect. Because it takes a certain amount of time for the phase-locked loop to generate a stable clock signal after it is set, this register is set to tell the chip how long it will take for the phase-locked loop to stabilize. Generally, we can keep the default value of this register.

LOCK TIME COUNT REGISTER (LOCKTIME)

Then, set the frequency division of HCLK and PCLK through CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER. Be sure to set the frequency division registers of these two first and then start setting MPLL and UPLL. This can prevent the clock frequency on the AHB and APB buses from being too fast. The register description is as follows:

CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER

The actual frequency division coefficient corresponding to the HDIVN setting value also depends on the 8th and 9th bits of the CAMDVN register. When powered on, these two bits default to 0.

Before setting UCLK and FCLK, we must first set the CPU bus to enter asynchronous working mode, so that FCLK can be used as the CPU working clock source when HDIVN is not 0. The official manual provides the assembly code for the CPU to enter asynchronous mode, the code is as follows:

/* Set the CPU to work in asynchronous mode */

mrc p15,0,r0,c1,c0,0

orr r0,r0,#0xc0000000 //R1_nF:OR:R1_iA

mcr p15,0,r0,c1,c0,0

Finally, set UPLL and MPLL to set UCLK and MCLK. According to the instructions in the manual, UCLK should be set before FCLK, so first configure the UPLLCON register, and then configure the MPLLCON register. The descriptions of the two registers are as follows:

PLL CONTROL REGISTER (MPLLCON & UPLLCON)

The desired frequency can be calculated by combining the register bit terminals MDIV, PDIV, and SDIV. However, the official provides a set of values ​​corresponding to common frequencies for ease of use. If you want to calculate manually, you can also use the formula provided in the manual to calculate it yourself. The official reference values ​​are as follows:

PLL VALUE SELECTION TABLE

3. Clock tree configuration reference assembly code

.text.global _start

_start:

/* Disable watchdog */

ldr r0, =0x53000000

ldr r1, =0str r1, [r0]

/* Set MPLL, FCLK : HCLK : PCLK = 400m : 100m : 50m */

/* LOCKTIME(0x4C000000) = 0xFFFFFFFF */

ldr r0, =0x4C000000

ldr r1, =0xFFFFFFFFstr r1, [r0]

/* CLKDIVN(0x4C000014) = 0X5, tFCLK:tHCLK:tPCLK = 1:4:8 */

ldr r0, =0x4C000014

ldr r1, =0x5str r1, [r0]

/* Set the CPU to work in asynchronous mode */

mrc p15,0,r0,c1,c0,0

orr r0,r0,#0xc0000000 //R1_nF:OR:R1_iA

mcr p15,0,r0,c1,c0,0

/* Set MPLLCON(0x4C000004) = (92<<12)|(1<<4)|(1<<0) 

 * m = MDIV+8 = 92+8=100

 * p = PDIV+2 = 1+2 = 3

 * s = SDIV = 1

 * FCLK = 2*m*Fin/(p*2^s) = 2*100*12/(3*2^1)=400M

 */

ldr r0, =0x4C000004

ldr r1, =(92<<12)|(1<<4)|(1<<0)

str r1, [r0]

/* Once the PLL is set, the lock time will be locked until the PLL output is stable* and then the CPU will work at the new frequency FCLK*/

/* Set up memory: sp stack */

/* Distinguish whether it is NOR/NAND startup

 * Write 0 to address 0, then read it out

 * If you get 0, it means the content at address 0 has been modified, it corresponds to ram, this is nand boot

 * Otherwise, it is NOR start

 */

mov r1, #0

ldr r0, [r1] 

/* Read out the original value backup */

str r1, [r1] /* 0->[0] */ 

ldr r2, [r1] /* r2=[0] */

cmp r1, r2 /* r1==r2? If they are equal, it means NAND boot*/

ldr sp, =0x40000000+4096 /* Assume that it is NOR startup*/

moveq sp, #4096 /* nand start */

streq r0, [r1] /* restore the original value */

bl main

halt:b halt