Bare metal series——nandflash

I have read the nandflash manual and other materials for a long time. Because of my poor English, I am a little confused when reading the manual. Fortunately, there are abundant resources on the Internet. I will summarize my understanding of nandflash operation. Due to some other reasons, I will not continue bare metal programming for the time being, but just write down all my understanding in detail.

1. First of all, there are three aspects for nandflash programming

   1. nandflash memory, of course this is the key point, because nandflash programming is to read, write, erase and other operations on nandflash.

   2. nandflash controller, S3C2440 has been integrated here, and what we can see is a bunch of registers. For 2440 programming, it is often necessary to set a bunch of registers and perform timing operations on the device.

   3. Pin configuration of nandflash, because the IO of 2440 is generally a multi-function multiplexed IO port.

2. Then the second aspect is the structure and operation of nandflash

1. The manual of a specific nandflash chip will give the structure of the chip. The nandflash is divided into two parts: main area and spare area. The main area stores data, and the spare area stores additional information, bad block ECC check, etc. The structure of NAND FLASH is that one piece of Nand flash is a device, 1 (Device) = xxxx (Blocks), 1 (Block) = xxxx (Pages), 1 (Page) = 528 (Bytes) = data block size (512Bytes) + OOB block size (16Bytes, data block is the main area, OOB is the spare area, except for the sixth byte of OOB, usually at least the first 3 bytes of OOB are stored in the Nand Flash hardware ECC code). As for the OOB area, each Page has it. If the NAND page size is 512 bytes, 16 bytes of OOB are allocated to each page; if the NAND is physically 2K pages, 64 bytes of OOB are allocated to each page. For detailed allocation, please refer to the data sheet.

2. Bad blocks. If there are no bad blocks in nand flash, it would be perfect. However, the process of nand flash determines that bad blocks are inevitable (the specific reason should be related to its storage method). It is precisely because of the existence of bad blocks that the use of nand storage becomes complicated. First of all, the definition of bad blocks refers to the existence of one or more uncertain states in a block.

3. Classification of bad blocks. There are two types of bad blocks. One is the bad blocks that already exist when leaving the factory, which are inherent bad blocks. For inherent bad blocks, the chip manufacturer has marked the bad blocks. The marking places are different for different chips. For example, the small one of Sangsun Company is 1page 512byte. The bad block checks the sixth byte of SPARE DATA.

The largest is 1page 2048byte, and the bad block checks the first byte of SPARE DATA. Generally, the sixth byte or the first byte of the first and second pages of each block is not 0xff and is generally written as 0. The second is the bad block that appears during use. For this part of the bad blocks, you need to create a bad block table to mark and manage them.

4. Bad block management. First of all, pay attention to the management of bad blocks. Nandflash reads and writes pages and erases blocks. Erasing may erase the bad block mark, so you must first determine whether it is a bad block before operation. There is a good idea on the Internet about the management of bad blocks. I think it is very good. The entire nandflash is divided into three areas. The first area uses information (including bad block table, number of blocks used, etc., and 10 blocks are reserved), the second area is the data recording area, and the third area is the bad block mapping area (dedicated to replacing bad blocks, it is a reserved area, data cannot be written directly into it, and it is 128 blocks).

Select a good block from the first 10 blocks to record the bad block information and other information of the entire nand, then the second area is the real data recording area, and the third area is the replacement area for the bad block. Before starting, run a bad block scanning program to build the entire bad block table, and the bad blocks generated later will also be recorded in the bad block table. When writing data again, first check the bad block table to see if it is a bad block. If it is a bad block, the data will be written to the block in the replacement area.

5. ECC Let me take Samsung's K9F2G08U0A nandflash as an example to explain my understanding. First of all, ECC is a verification method for error detection and correction. The principle is relatively complicated. Samsung has a document that can be implemented with software and hardware. S3C2440 hardware generates ECC, which simplifies programming. ECC is divided into two parts: one is the ECC for the main data area, and the other is the ECC for the spare area. The process of ECC verification is as follows: first, after reading and writing a page of data, the hardware automatically generates ECC data to NFMECCD0/1 (main area data ECC), and after reading and writing the spare area, it automatically generates ECC to NFSECCD0/1 (spare area data ECC). Then we need to save these two ECC data to the spare area of ​​nand. For K9F2G08U0A, the spare area has 64 bytes. Do not use the 1st and 2nd bytes, because the bad block mark at the factory is saved in the first and second bytes of the first and second pages of each Block. For the sake of uniformity, when you encounter bad blocks in the future, you will also use one or two bytes to mark bad blocks. Use other bytes (choose by yourself) to save the ECC of the Main area and the ECC of the spare area. When reading the data of the main area, the hardware automatically generates ECC to the NFMECCD0/1 register, and then compares the last saved ECC data twice. If they are the same, there is no error. We only need to put the extracted ECC data into the register NFMECCD, and the hardware automatically compares it. I only need to read the ECC status register NFESTAT0/1 to get the result. Similarly, the spare is checked and the error is handled at the same time.

Supplement: I wrote a blog post yesterday, and I read some books today to supplement it.

First of all, my chip is K9F2G08U0B from sangsun. Well, the size of the chip is 256M 8-bit IO. The manual does not clearly state how many planes the entire chip is divided into, but after looking at the description at the back, I think the entire chip is divided into 2 planes.

Another important thing to correct is that the storage area of ​​nandflash consists of two parts, the main area and the spare area. In addition, nandflash also has a register - the status register. After completing the read and write operation, the status in nandflash is read through the read status register command to determine whether the read and write operation is successful. Note that this register is in nandflash, not in the nandflash controller. The meaning of the register value is explained in the back of the manual.