The power-on reset (POR) pulse is generated by the on-chip detection circuit. The detection level is shown in Table 20. Whenever VCC falls below the detection level, a POR occurs. The POR circuit can be used to trigger a reset or to detect a power failure.
The POR circuit ensures that the device is reset at power-on. The delay counter is triggered after VCC reaches the power-on threshold voltage. The device remains in reset state until the counter overflows. When VCC drops, as long as it is below the detection threshold, the RESET signal takes effect immediately.
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