ARM Basic Learning-Memory Management Unit MMU

In the ARM system, the memory unit MMU mainly completes the following tasks:

(1) Mapping of virtual storage space to physical storage space; ARM uses page-based virtual storage management, dividing the virtual space into blocks of fixed size, each block is called a page; the physical memory address space is also divided into pages of the same size; the page size is divided into coarse-grained and fine-grained; the MMU needs to implement the conversion from virtual address to physical address;

(2) Control of memory access rights;

(3) Setting the buffering characteristics of the virtual storage space;

The page table is an important means to implement MMU. The page table is stored in the memory. Each row of the table corresponds to a page in the virtual space. The row contains the address of the physical memory page corresponding to the virtual memory page. The base address of the page table is saved by register C2 of the CP15 coprocessor.

TLB

(1) Concept

During a period of program execution, access to the page table is limited to a few units. A memory with a smaller capacity and access speed comparable to that of a general register can be used to store the address translation entries required for the current access. This small-capacity page table is called a fast table, or TLB (Translation Lookaside Buffer).

When the CPU accesses the memory, it searches the TLB for the required address translation entry. If the entry does not exist, the CPU searches the page table in the memory and adds the corresponding result to the TLB. In this way, when the CPU needs the address translation entry again next time, it can get it directly from the TLB, which greatly speeds up the address translation.

When the page table content in the memory changes, or a new page table is used by modifying register C2 in CP15, the contents of the TLB need to be cleared. The MMU provides relevant hardware to support this operation. Register C8 in CP15 is used to control the related operations of clearing the TLB content.

The MMU can lock certain address translation entries in the TLB, so that the address translation speed associated with the address translation entry remains fast. In the MMU, C10 is used to control the locking of TLB contents.

Note: TLB stores address translation entries, which is equivalent to a small page table.

(2) TLB update change entry

a. Storage access process when MMU is enabled.

When the ARM processor requests a storage access, it first looks up the virtual address in the TLB. If the data TLB and instruction TLB are separate in the system, when fetching instructions, the corresponding virtual address is looked up from the instruction TLB, and for other memory access operations, the corresponding virtual address is looked up from the data TLB.

If the address translation entry corresponding to the virtual address is not in the TLB, the CPU will query it from the page table in the memory and add the corresponding result to the TLB. If the TLB is full, it needs to be replaced according to a certain elimination algorithm. In this way, when the CPU needs the address translation entry next time, it can get it directly from the TLB, which greatly speeds up the address translation.

After obtaining the required address change entry, the following operations will be performed

(1) Get the physical address corresponding to the virtual address;

(2) Determine whether to cache the result of the memory access based on the C (cache) control bit and the B (Bufferable) control bit in the entry;

(3) Determine whether the memory access is allowed based on the access permission control bit and the domain access control bit. If the memory access is not allowed, CP15 reports the storage access abort to the ARM processor.

(4) For storage accesses that do not allow caching, use the physical address obtained in step (1) to access the memory. For storage accesses that allow caching, if there is a cache hit, ignore the physical address; if there is a cache miss, use the physical address obtained in step (1) to access the memory and read the block of data into the cache.

b. Storage access process when MMU is disabled

When the MMU is disabled, whether the cache and write buffer are supported is determined by the design of each specific chip. If the chip specifies that the cache and write buffer are disabled when the MMU is disabled, storage access will not consider the C and B control bits. If the chip specifies that the cache and write buffer can be enabled when the MMU is disabled, then C=0 and B=0 for data access; when reading instructions, C=1 if a separate TLB is used, and C=0 if a unified TLB is used;

Storage access does not perform permission control, and the MMU does not generate a storage access abort signal;

All physical addresses and virtual addresses are equal, that is, flat mode is used;

c. Issues to note when disabling/enabling MMU

Before enabling the MMU, a page number table must be created in the memory and all related registers in CP15 must be initialized.

If the flat storage mode is not used (physical address and virtual address are equal), the correspondence between virtual address and physical address will change when disabling/enabling MMU. At this time, the current address translation entry in the cache should be cleared;

If the physical address and virtual address of the code that disables/enables the MMU are not the same, it will cause great trouble when disabling/enabling the MMU. Therefore, it is strongly recommended that the physical address and virtual address of the code that disables/enables the MMU be the same.

Virtual address mapping physical address principle

Most systems that use virtual memory use a mechanism called paging. The virtual address space is divided into units called pages. The corresponding physical address space is also divided into units called page frames. The size of the page and the page frame must be the same.

The virtual address is divided into two parts by the MMU: the first part is the page index, and the second part is the offset relative to the page head address;

When the CPU accesses an address, the address is a virtual address, so the address is sent to the MMU, and the MMU uses the high bits of the virtual address as the page number index to find the corresponding address translation entry in the page table. The page base address of the physical address is found from the address translation entry, and the offset in the virtual address is added to get the real physical address, and then the MMU sends the physical address to the address bus to access the physical memory.

Example: As shown in the figure, if the paging size is 1M and the virtual address is 0x30000012,

The binary code of the virtual address is 00110000 00000000 00000000 00010010. The first 12 bits are the page number index, and the last 20 bits are the offset, because 2^20 = 1M

The first 12 bits of the page number index is 00110000 0000 = 768, so the address with an offset of 768 relative to the page table base address is found in the page table, and then the address translation entry is obtained. So 0x0300 << 20 bits, the physical page base address is obtained, and the offset bits in the virtual address 0000 00000000 00010010 = 0x12 are added to get the real physical address 0x30000012.

Address translation process in MMU

In ARM, there are two ways to map virtual addresses to physical addresses: primary mapping and secondary mapping.

(1) First-level mapping

When using level 1 mapping, only one page table is used, which we call the level 1 page table, denoted by L1. In level 1 mapping, the virtual space is divided into segments, each of which is 1M in size. The corresponding physical space is also divided in this way, with the unit being the segment frame, and the size of the segment and segment frame must be the same.

First, we create a page table in memory (this page table is created by ourselves). Each item in the page table stores a physical segment base address, the access rights and buffer characteristics of the page, etc. The size of each item in the page table is 4 bytes, so the address of each item is word-aligned. We call each cell in the page table an item.

Because the addressable range of ARM is 4G, and the size of each segment of virtual space is 1M, as shown in the figure, the page table has 4096 entries. Each entry corresponds to a segment, and each entry stores a physical segment base address, the page's access rights and buffering characteristics, etc.

The virtual address is divided into two parts by the MMU. The first part is the page index number (bits[31:20]), and the second part is the offset relative to the physical address (bits[0:19]).

So when accessing an address, this address is a virtual address. The MMU will use the page table base address + page index number in the C2 register of the coprocessor CP15 to find the corresponding item in the page table, find the physical segment base address from the corresponding item in the page table, and then: physical segment base address + offset (this is the second part of the virtual address) = physical address.

example:

The CPU wants to access the address 0x300008, which is a virtual address. The MMU will find the entry with an offset of 0x3 relative to the page table base address based on the page index number (that is, 0x3). The physical segment base address in this entry is 0x006.

Physical address = (0x006<<20) + 0x8 = 0x600008

　b. Secondary mapping

When using the second-level mapping, the first-level page table L1 still exists, but the first-level page table no longer stores the physical segment base address. Instead, it stores the base address of the second-level page table, that is, the first address of the second-level page table.

The first-level page table must represent an address range of 4G, with a total of 4096 items, each of which represents a size of 1M. The second-level page table is equivalent to a more detailed division of the 1M range of the first-level page table, so each second-level page table must represent an address range of 1M.