arm clock (CLOCK) and power management (POWER MANAGEMENT)

ARM architecture: ARM920T

1. Overview:
The relationship between clock and power management:
    The power management module uses software to control the system clock to reduce power consumption in ARM920T. These schemes
are related to PLL, clock control logic (FCLK, HCLK and PCLK) and wake-up signals.

The clock and power management module consists of three parts: clock control, USB control and power control.
1. Clock control logic The
clock control logic in ARM920T can generate the necessary clock signals, including FCLK of CPU, HCLK of AHB bus peripherals and PCLK of APB bus peripherals.
ARM920T contains two phase-locked loops (PLL): one (MPLL) provides FCLK, HCLK and PCLK, and the other (UPLL) is dedicated to the USB module (48MHz). The
    clock control logic can slow down the clock without using PLL, and the clocks of various peripheral modules can be connected or disconnected by software to reduce power consumption.

2. USB clock control
        Both the USB host interface and the USB device interface require a 48MHz clock. In arm920t, the USB dedicated PLL (UPLL) generates 48MHz for USB.
        UCLK is not provided before the PLL (UPLL) is configured.

3. Power control logic
arm920t includes various power management schemes to ensure optimal power consumption for a given task. The power management module in arm920t
can be activated in four modes: normal (NORMAL) mode, slow (SLOW) mode, idle (IDLE) mode and sleep (SLEEP) mode.

    The relationship is as follows:
      
    1. Note:
    The main clock source comes from an external crystal oscillator (XTIpll) or an external clock (EXTCLK). The clock generation includes an oscillator (Oscillation Amplifier, OSC) connected to an external crystal oscillator, and also contains two PLLs (phase-locked loops) required by arm920t for generating high-frequency clocks.

    2. Note:
        The pin signals of the arm920t core used for clock and power management

        Note: nRSTOUT, PWREN, OM[3:2], CLKOUT[1:0]

    3. Note:
         (1) In NORMAL mode, FCLK = Mpll;
         (2) In SLOW mode (just powered on or reset), FCLK = (crystal or EXTCLK) / division factor.
            The default operating frequency of the CPU is 12MHz or 16.9344MHz, and 12M is the most commonly used.

     

    Related registers:
    
2. Clock control logic
     1, PLL, FCLK, HCLK, PCLK
The clock control logic in arm920t can generate the necessary clock signals, including the FCLK of the CPU, the HCLK of the AHB bus peripherals, and the PCLK of the APB bus peripherals.
    FCLK is the clock provided to ARM920T. HCLK is 
    the clock provided to the AHB bus for ARM920T, memory controller, interrupt controller, LCD controller, DMA and USB host module. 
    PCLK is the clock provided to the APB bus for peripherals such as WDT, IIS, I2C, PWM timer, MMC/SD interface, ADC, UART, GPIO, RTC and SPI. 

arm920t contains two phase-locked loops (PLL): one (MPLL) is provided to FCLK, HCLK and PCLK, and one (UPLL) is dedicated to the USB module (48MHz).
    The clock control logic can not use PLL to slow down the clock, and the clocks of various peripheral modules can be connected or disconnected by software to reduce power consumption.

    Contains two phase-locked loops MPLL and UPLL to generate clocks of different frequencies required by the system.
    MPLL:
        generates FCLK clock for CPU
        and HCLK clock for AHB and
        PCLK clock for APB.
    UPLL:
        generates UCLK (48MHz) for USB (Host and Device)
     
    
     . 2. Relationship between PLL and FCLK
   
         (1) In NORMAL (PLL enabled) mode, FCLK=Mpll;
         (2) In SLOW mode (just powered on or reset, PLL not enabled), FCLK=(crystal or EXTCLK)/frequency division factor.
            The default operating frequency of the CPU is 12MHz or 16.9344MHz, and 12M is the most commonly used here. Phase-

        locked loop output frequency (Mpll and Upll have different calculation methods)
        Mpll =(2*m*Fin) / (p*2^S)
        Upll =(m * Fin) / (p * 2^S) 

                Fin refers to the frequency of the crystal oscillator itself connected to the CPU periphery, usually 12MHz.

                m = MDIV + 8, 

                p = PDIV + 2,  

                s = SDIV.

            Note: When you set the values ​​of MPLL and UPLL, you must first set the UPLL value and then set the MPLL value. (About 7 NOP intervals are required)

          

            Main oscillator circuit:
          

            Select the clock source through the OM[3:2] pin of the arm920t core:
           
            Note:
            1. Although MPLL starts after reset, the MPLL output (Mpll) is not used as the system clock until the software writes a valid value to set the MPLLCON register.
                Before setting this value, the clock provided by the external crystal or external clock source is directly used as the system clock. Even if the user does not want to change the default value of the MPLLCON register
                , the user should write the same value to the MPLLCON register.
                Common mode: OM[3:2] = 00  
            2. OM[3:2] is used to determine a test mode when OM[1:0] is 11


     3. The relationship between FCLK, HCLK, PCLK
        

    HDIVN, PDIVN:
        

    HCLK3_HALF, HCLK4_HALF:
      


3. USB clock control         
        Both the USB host interface and the USB device interface require a 48MHz clock. In arm920t, the USB dedicated PLL (UPLL) generates 48MHz for USB.
        UCLK is not provided before configuring the PLL (UPLL).


Power control logic
arm920t includes various power management schemes to ensure optimal power consumption for a given task. The power
management module in arm920t can be activated into four modes: normal (NORMAL) mode, slow (SLOW) mode, idle (IDLE) mode and sleep (SLEEP) mode.
         
        Normal mode:
            1. Phase-locked loop (PLL) works
            2. Provides clocks for CPU and all on-chip peripherals
            3. This mode has the highest system power consumption
            4. It allows users to control the operation of peripherals by software. For example, if a timer is not necessary,
                the user can disconnect the clock connected to the timer (CLKCON register) to reduce power consumption. 
        Slow mode:
            1. Phase-locked loop does not work
            2. CPU directly uses the original clock or the frequency division of the original clock. The low clock frequency in this mode reduces power consumption, and the non-operation of the phase-locked loop also reduces power consumption
            3. In this mode, power consumption depends only on the frequency of the external clock. The power consumption caused by the PLL is excluded. 

        Note: PLL can only be turned off in SLOW mode. If the PLL is turned off in other modes, MCD does not ensure that the PLL operates normally.
           
           
        4. Mode conversion
            (1). After the MPLL is started, it takes a period of time (LockTime) for the MPLL output to stabilize.
          
        
            (2) To switch from NORMAL mode to SLOW mode,
            set bit[4]SLOW_BIT=1 in the CLKSLOW register.
             

            (3) To switch from SLOW mode to NORMAL mode
                @1@ Before the MPLL output is stable (before the lock time),
                    if the user switches from SLOW mode to NORMAL mode by disabling both the SLOW_BIT and MPLL_OFF bits in the CLKSLOW register after the PLL lock time
                    , the frequency will change only after the PLL lock time.
                    
                @2@ After the MPLL output is stable (after the lock time),
                    if the user switches from SLOW mode to NORMAL mode by disabling the SLOW_BIT in the CLKSLOW register after the PLL lock time,
                    the frequency will change only after the SLOW mode is disabled.
                   

        Idle mode:
            1. Stop supplying clock to the CPU. The CPU does not work (all its peripherals work).
            2. Exit method: Any interrupt request can wake up the CPU and exit idle mode.
            3. This module only disconnects the clock (FCLK) of the CPU core, but it provides clocks to all other peripherals.
                Idle mode results in reduced power consumption due to the CPU core. Any interrupt request to the CPU can wake it up from idle mode. 
            
            4. How to enter idle mode:
                Set bit [2] IDLE BIT of the clock generation control register (CLKCON) to 1 to enter idle mode. This bit will not be automatically cleared.

        Sleep mode:
            1. The clock module is powered off. All parts except the wake-up circuit are not powered.
            2. The system needs to be powered in two parts. This mode has the lowest power consumption.
            3. Exit method: To use interrupt wake-up, an external interrupt must be set
                (1) External interrupt EINT0---15
                (2) Real-time clock alarm interrupt
            4. This module is separated from the internal power supply. Therefore, in this mode, no power is generated by the CPU and other parts except the wake-up logic.
                Power consumption of internal logic. To activate sleep mode, two independent power supplies are required. One of the two power supplies provides power to the wake-up logic.
                The other provides power to other internal logic including the CPU, and should be able to control the power on and off. In sleep mode,
                the second power supply for the CPU and internal logic will be turned off. It can be woken up from sleep mode by EINT[15:0] or RTC alarm interrupt.

            5. Enter sleep (SLEEP) mode
                1. Set GPIO configuration properly for sleep mode. 
                2. Mask all interrupts in the INTMSK register. 
                3. Configure wake-up sources including RTC alarm properly. (It is not necessary to mask the corresponding bits of the wake-up source in EINTMASK,
                        in order to enable the corresponding bits of SRCPND or EINTPEND to be set. However, if the wake-up source is triggered and the corresponding bits of EINTMASK are masked,
                        wake-up will occur but the corresponding bits of SRCPND or EINTPEND will not be set.) 
                4. Set the USB port to suspend mode (MISCCR[13:12]=11b). 
                5. Save some special meaning values ​​to GSTATUS[4:3] registers. These registers are protected during sleep mode. 
                6. Configure MISCCR[1:0] for the pull-up resistor of data bus D[31:0]. If there is an external bus holder, such as 74LVCH162245,
                        turn off the pull-up resistor. If there is no pull-up resistor, turn on the pull-up resistor. In addition, the memory related pins are set to two types, and the other is inactive. 
                7. Clear LCDCON1.ENVID bit to stop LCD. 
                8. Read rREFRESH and rCLKCON registers to fill TLB. 
                9. Set REFRESH[22]=1b to make SDRAM enter self-refresh mode. 
                10. Wait until SDRAM self-refresh is valid. 
                11. Set MISCCR[19:17]=111b to make SDRAM signals (SCLK0, SCLK1 and SCKE) protected during sleep mode. 
                12. Set the sleep mode bit in the CLKCON register.
               

            6. Wake up from sleep mode
                1. If one of the wakeup sources is triggered, an internal reset signal will be issued. It will be the same as if the external nRESET pin was triggered. The
                        duration of this reset is determined by the internal 16-bit control logic and the reset trigger time calculated by tRST = (65535 / XTAL_Frequency). 
                2. Check GSTATUS2[2] to see if it was power-on that caused the wakeup from sleep mode. 
                3. Set MISCCR [19:17] = 000b to release the SDRAM signal protection. 
                4. Configure the SDRAM memory controller. 
                5. Wait until the SDRAM self-refresh is released. Usually SDRAM requires a cycle to refresh all SDRAM rows. 
                6. The information in GSTATUS[3:4] can be used for the user's own purposes, because the value in GSTATUS[3:4] is protected during sleep mode. 
                7. For EINT[3:0], check the SRCPND register. 
                        For EINT[15:4], check EINTPEND instead of SRCPND (SRCPND will not be set although some bits of EINTPEND will be set).

            7. Power control in sleep mode
                @1@ In sleep mode, VDDi, VDDiarm, VDDMPLL and VDDUPLL are all turned off by controlling the PWREN pin.
                @2@ If the PWREN signal is activated (high level), VDDi and VDDiarm will be provided by an external voltage regulator.
                        If the PWREN pin is inactive (low level), VDDi and VDDiarm will be turned off. 
                Note: 
                    Even if VDDi, VDDia rm, VDDMPLL and VDDUPLL may be turned off, they should be provided to other power pins
                

            8. Wake-up condition in sleep mode
                @1@ A level signal or edge signal appears on the EINTn input pin and is confirmed.
                @2@ The EINTn input pin is configured as an external interrupt.
                @3@ nBATT-FLT bit is high.
                Note: Once woken up, the corresponding EINTn pin will no longer be used for wakeup, that is, this pin can be used as an external interrupt source again.

            9. Sleep mode and pull-up resistor of data bus 
                In sleep mode, the data bus (D[31:0] or D[15:0]) can be selected as high impedance or output low level. 
                The data bus can be set to high impedance with pull-up resistor turned on or set to output low level with pull-up resistor turned off to reduce power consumption in sleep mode.
                    The pull-up resistor of the D[31:0] pin is controlled by the GPIO control register (MISCCR). However, if there is an external bus holder,
                    such as 74LVCH162245 on the data bus, the user can select one of two states: one is the output low level with the pull-up resistor turned off, and
                    the other is the high impedance state with the pull-up resistor turned off, both of which are low power consumption.

            10. Sleep mode and output port status 
                The output port should be set to a reasonable logic level in the power-off mode to minimize current consumption. If the output port pin is not connected to a load, a high level is preferred.
                If the output is low, the internal parasitic resistance will consume current; if the output is high, no current will be consumed.
                As an output port, if the output state is high, the current consumption will be reduced. It is recommended to set the output port to output high level in sleep mode.

            11. Battery fault signal (nBATT_FLT)
                 The nBATT_FLT pin has the following two functions. 
                (1) When the CPU is not in sleep mode, the nBATT_FLT pin will cause an interrupt request by setting BATT_FUNC(MISCCR[22:20]) to 10x'b.
                        The interrupt type of nBATT_FLT is triggered when it is low. 
                (2) When the CPU is in sleep mode, the issuance of nBATT_FLT will disable wakeup from sleep mode by setting BATT_FUNC(MISCCR[22:20]) to 11x'b.
                        Therefore, any wakeup source will be blocked. If nBATT_FLT is set, it is to protect the system from low battery failure. 

                Miscellaneous Control Register (MISCELLANEOUS CONTROL REGISTER, MISCCR)
                
                

            12, ADC Power Down 
                ADC contains an additional power down bit [2] STDBM in the ADCCON register.
                If the arm920t enters sleep mode, the ADC should enter its own power down mode.