ARM startup and working mode switching

In the ARM system, there are usually three ways to control the execution flow of the program:

During normal program execution, the value of the program counter register (PC) increases by 4 bytes for each ARM instruction executed; the value of the program counter register (PC) increases by 2 bytes for each Thumb instruction executed. The entire process is executed sequentially.

Through the jump instruction, the program can jump to a specific address mark for execution, or jump to a specific subroutine for execution. Among them, the B instruction is used to perform a jump operation; the BL instruction saves the return address of the subroutine while executing the jump action; the BX instruction can switch the program state to Thumb state according to the lowest bit of the target address while executing the jump operation; the BLX instruction performs 3 operations: jump to the target address for execution, save the return address of the subroutine, and switch the program state to Thumb state according to the lowest bit of the target address.

When an abnormal interrupt occurs, the system will jump to the corresponding abnormal interrupt handler after executing the current instruction. After the abnormal interrupt handler is executed, the program returns to the next instruction of the instruction where the interrupt occurred. When entering the abnormal interrupt handler, the execution scene of the interrupted program must be saved, and when exiting from the abnormal interrupt handler, the execution scene of the interrupted program must be restored. This article discusses the abnormal interrupt mechanism in the ARM system.

Types of abnormal interrupts in ARM system:

The abnormal interrupts in the ARM system are introduced as follows.

Reset: When the processor's reset pin is valid, the system generates a reset exception interrupt, and the program jumps to the reset exception interrupt handler for execution. Reset exception interrupts are usually used in the following two situations: when the system is powered on, when the system is reset, it jumps to the reset interrupt vector for execution, which is called a soft reset.

Undefined instruction: When the ARM processor or the coprocessor in the system considers the current instruction to be undefined, an undefined instruction exception interrupt is generated. This exception interrupt mechanism can be used to simulate floating-point vector operations.

Software interrupt: This is an interrupt instruction defined by the user. It can be used by programs in user mode to call privileged operation instructions. In real-time operating systems (RTOS), this mechanism can be used to implement system function calls.

Instruction prefetch abort: If the address of the instruction prefetched by the processor does not exist, or the address does not allow the current instruction to access, the processor generates an instruction prefetch abort exception interrupt when the prefetched instruction is executed.

Data access abort: If the target address of a data access instruction does not exist, or the address does not allow the current instruction to access it, the processor generates a data access abort exception interrupt.

External interrupt request (IRQ): When the processor's external interrupt request pin is valid and the I control bit in the CPSR register is cleared, the processor generates an external interrupt request exception interrupt. Each peripheral in the system usually requests processor service through this exception interrupt.

Fast interrupt request (FIQ): When the processor's external fast interrupt request pin is valid and the F control bit in the CPSR register is cleared, the processor generates an external interrupt request (FIQ) exception interrupt.

Exception interrupt vector table and exception interrupt priority:

The exception vector table specifies the correspondence between the exception interrupt and its handler. It is usually stored at the lower end of the storage address. In the ARM system, the size of the exception interrupt vector table is 32 bytes. Among them, each exception interrupt occupies 4 bytes, and 4 bytes of space are reserved.

The 4-byte space in the interrupt vector table corresponding to each abnormal interrupt stores a jump instruction or a data access instruction that assigns a value to the PC register. Usually, for these two instructions, the program will jump to the corresponding abnormal interrupt handler for execution.

When several exception interrupts occur at the same time, they must be processed in a certain order. In ARM, this processing order is achieved by assigning certain priorities to exception interrupts. Of course, some exception interrupts cannot occur at the same time, such as instruction prefetch abort exceptions and soft interrupts (SWI) exception interrupts are triggered by the execution of the same instruction, and they cannot occur at the same time. When the processor executes a specific exception interrupt, it is called the processor is in a specific interrupt mode. The interrupt vector address of each exception interrupt and the interrupt processing priority are shown in the following table.

Registers used by exception interrupts:

Each exception interrupt corresponds to a certain processor mode. Applications usually run in user mode. The processor modes in ARM are shown in the following table.

Different processor modes may have corresponding physical register groups, as shown in the following table. R13_svc represents the R13 register in privileged mode, R13_abt represents the R13 register in abort mode, and the meanings of the remaining register names are similar.

If the exception interrupt handler uses other registers other than its own physical registers, the exception interrupt handler must save and restore these registers. The physical register names in the above table are not predefined in the ARM assembly. When the user uses these registers, the pseudo operation RN must be used to define these names. For example, the register name R13_svc can be defined by the following operation:

R13_svc RN R13

The process of entering and exiting an abnormal interrupt:

The following describes the processor's response to various exception interrupts and the method of returning from the exception interrupt handler. For different exception interrupt handlers, the return address and the instructions used are different.

The ARM processor responds to abnormal interrupts as follows:

(1) Save the current state of the processor, the interrupt mask bit, and each conditional flag bit. This is achieved by saving the contents of the current program status register CPSR to the SPSR register corresponding to the exception interrupt to be executed. Each exception interrupt has its own physical SPSR register.

(2) Set the corresponding bit in the current program status register CPSR. This includes setting the bit in CPSR to make the processor enter the corresponding execution mode; setting the bit in CPSR to disable IRQ interrupts. When entering FIQ mode, IRQ interrupts are disabled.

(3). Set register lr_mode to the return address.

(4) Set the program counter (PC) value to the interrupt vector address of the exception interrupt, thereby jumping to the corresponding exception interrupt handler for execution.

The above-mentioned processor's response process to the abnormal interrupt can be described by the following pseudo code.

R14_ = return link

SPSR_ = CPSR

CPSR[4:0] = exception mode number

/* When running in ARM state*/

CPSR[5] = 0

/* When the corresponding FIQ is interrupted abnormally, disable new FIQ interrupts*/

if == RESET or FIQ then

CPSR[6] = 1

/* Disable new FIQ interrupts */

CPSR[7] = 1

PC = exception vector address

1. Respond to reset exception interrupt

When the processor's reset pin is valid, the processor terminates the current instruction. When the processor's reset pin becomes invalid, the processor starts executing the following operations.

R14_svc = UNPREDICATBLE value

SPSR_svc = UNPREDICATBLE value

/* Enter privileged mode */

CPSR[4:0] = 0b10011

/* Switch to ARM state */

CPSR[5] = 0

/* Disable FIQ exception interrupt */

CPSR[6] = 1

/* Disable IRQ interrupt */

CPSR[7] = 1

if high vectors configured then

PC = 0XFFFF0000

else

PC = 0X00000000

2. Respond to undefined instruction exception interrupt

The processing procedure when the processor responds to an undefined instruction exception interrupt is shown in the pseudo code below.

R14_und = address of next instruction after the undefined instruction

SPSR_und = CPSR

/* Enter undefined instruction exception interrupt */

CPSR[4:0] = 0b11011

/* Switch to ARM state */

CPSR[5] = 0

/* CPSR[6] remains unchanged*/

/* Disable IRQ abnormal interrupt */

CPSR[7] = 1

if high vectors configured then

PC = 0xFFFF0004

else 

PC = 0x00000004

3. Respond to SWI exception interrupt

The processor's response to the SWI exception interrupt is shown in the pseudo code below.

R14_svc = address of next instruction after the SWI instruction

SPSR_svc = CPSR

/* Enter privileged mode */

CPSR[4:0] = 0b10011

/* Switch to ARM state */

CPSR[5] = 0

/* CPSR[6] remains unchanged*/

/* Disable IRQ abnormal interrupt */

CPSR[7] = 1

if high vectors configured then

PC = 0xFFFF0008

else 

PC = 0x00000008

4. Response to instruction pre-termination exception interrupt

The processing procedure of the processor in response to the instruction prefetch abort exception interrupt is shown in the pseudo code below.

R14_abt = address of the aborted instruction+4

SPSR_abt = CPSR

/* Enter instruction prefetch abort mode */

CPSR[4:0] = 0b10111

/* Switch to ARM state */

CSPR[5] = 0

/* CPSR[6] remains unchanged*/

/* Disable IRQ abnormal interrupt */

CPSR[7] = 1

if high vectors configured then

PC = 0xFFFF000C

else 

PC = 0x0000000C

5. Respond to data access abort exception

The processing procedure of the processor in response to the data access abort exception interrupt is shown in the pseudo code below.

R14_abt = address of the aborted instruction+8

SPSR_abt = CPSR

/* Enter data access abort */