S5PV210 interrupt system and key control external interrupt

(1) When processing interrupts, you should pay attention to protecting the scene (if the interrupt comes from SVC mode, save the values ​​of the necessary registers in SVC mode) and restoring the scene (after the interrupt is processed, before returning to SVC mode, restore the values ​​of the necessary registers in SVC mode. Otherwise, the values ​​of the registers will be messed up after returning to SVC mode, and the regular tasks that were originally being performed in SVC mode will be damaged by you)

(2) Saving the scene includes: first, setting up the IRQ stack; second, saving LR; third, saving R0~R12

(3) Why do we need to save the LR register? We need to consider the issue of interrupt return. After the interrupt ISR is executed, how do we return to SVC mode and continue to execute the original code? Interrupt return actually depends on how we save the scene when we enter the interrupt. The two key registers when the interrupt returns are PC and CPSR. Therefore, when we enter the IRQ mode, we should save the address of the next instruction in SVC mode (interrupt return address) and CPSR, so that when we restore in the future, we can give the interrupt return address to PC and the saved CPSR to CPSR.

(4) The interrupt return address is stored in LR, and the CPSR is (automatically) stored in SPSR (in IRQ mode).

4. Compile and save the scene and restore the scene

(1) The key to protecting the scene is to save: the return address of the interrupt handler, r0-r12 (cpsr is automatically saved)

(2) The recovery site mainly restores: r0-r12, pc, cpsr registers

Interrupt handling in start.s:

/*

 * File name: start.S

 * Description: Add interrupt handling assembly function

 */

#define WTCON 0xE2700000

#define SVC_STACK 0xd0037d80

#define IRQ_STACK 0xd0037f80 //The address of the stack in IRQ mode (full reduction stack is used here)

.global _start

.global IRQ_handle

// Change the _start link attribute to external so that other files can see _start

_start:

// Step 1: Turn off the watchdog (write 0 to bit 5 of WTCON)

ldr r0, =WTCON

ldr r1, =0x0

str r1, [r0]

// Step 2: Initialize the clock

bl clock_init

// Step 3: Set up the SVC stack

ldr sp, =SVC_STACK

// Step 4: Turn icache on/off

mrc p15,0,r0,c1,c0,0; // Read c1 of cp15 to r0

//bic r0, r0, #(1<<12) // bit12 set to 0 to disable icache

orr r0, r0, #(1<<12) // bit12 set to 1 to enable iCache

mcr p15,0,r0,c1,c0,0;

bl main

// From here you can start calling C programs

//bl led_blink // led_blink is a function implemented in C language

// The final infinite loop in the assembly cannot be lost

b .

// In this assembly function, it is used to save and restore the scene in interrupt mode, and call the real interrupt handler

IRQ_handle:

// Set up the stack in IRQ mode

ldr sp, =IRQ_STACK //Enter IRQ mode and set the stack in IRQ mode

// Save LR

// Because ARM has a pipeline, the value of PC will be +8 compared to the actual executed code.

sub lr, lr, #4

// Save r0-r12 and lr to the stack in irq mode

stmfd sp!, {r0-r12, lr}

//Call the real isr here to handle the interrupt

bl irq_handler

// After the processing is completed, the scene is restored. In fact, it is to return from interruption. The key is to restore r0-r12, pc, and cpsr together.

ldmfd sp!, {r0-r12, pc}^

3. S5PV210 vector interrupt controller

1. Two stages of exception handling

(1) Exception handling can be understood in two stages. The first stage is the exception vector table jump; the second stage is entering the actual exception handling program.

The part after irq_handler.

2. Review: The first stage of interrupt processing (exception vector table stage) processing.

(1) The first stage is able to proceed mainly due to the exception vector table mechanism provided by the CPU design. The main tasks of the first stage are from the occurrence of an exception to responding to the exception and saving the scene, jumping to the actual exception handler, and restoring the scene.

(2) The purpose of the second stage is to identify which of the multiple interrupt sources has caused an interrupt, and then call the corresponding interrupt handler to handle the interrupt.

3. The second stage of S3C2440 processing

(1) The first question is how to find the specific interrupt: There is a register (32 bits) in the interrupt controller of S3C2440. Each bit of the register corresponds to an interrupt source. (In order to support more interrupt sources, 2440 also designed a sub-interrupt mechanism. In the first-level interrupt register, some interrupts share a common bit, such as AC97 and WDT. For shared interrupts, sub-interrupts are used to distinguish which interrupt occurred.)

(2) The second question is how to find the corresponding isr: First, each interrupt is numbered. After entering isr_handler, the interrupt number is determined by checking the interrupt source register and the sub-interrupt register (which bit is 1). Then, this number is used to look up the isr array (the isr array is pre-set when the interrupt is initialized, that is, the function names of the isr of each interrupt are organized into an array, and the number corresponding to the interrupt is used as an index to query this array) to obtain the isr address.

Evaluation: The interrupt handling design of 2440 is not particularly good: it is very troublesome to use sub-interrupts to make it 2-level in the first process; it is troublesome to calculate the interrupt number in the second process, which is very time-consuming. The time for interrupt processing is very precious (the system has a performance indicator called real-time. Real-time is the time from the interrupt to the response, and the shorter this time, the better.)

4. The second stage of S5PV210 processing

(1) The first question is how to find the specific interrupt: S5PV210 supports many interrupt sources, so it directly designs 4 interrupt registers, each with 32 bits, and each bit corresponds to an interrupt source. (Theoretically, 210 supports up to 128 interrupts, but actually supports less than 128, and some bits are empty); 210 does not have sub-interrupt registers, and each interrupt source is parallel at the same level. When an interrupt occurs, query the 4 interrupt source registers in irq_handler in turn to see which bit is set to 1. If the register corresponding to this bit has an interrupt, the interrupt number has been found.

(2) The second problem is how to find the corresponding ISR: 210 supports many more interrupt sources. If we still use the 2440 method to find the ISR address, it will be too slow and affect real-time performance. Therefore, 210 has developed a new mechanism for finding ISRs. 210 provides many registers to solve the problem of finding the corresponding ISR for each interrupt source. The specific search process and establishment process are shown in the next section. The effect is that when a corresponding interrupt occurs, the hardware will automatically push the corresponding ISR into a certain register, and our software only needs to execute the function in this register.

5. Summary: The first stage is the same, the second stage is different

(1) The first stage (the exception vector table stage) is almost identical between the 2440 and 210. In fact, almost all CPUs are identical in the first stage.

(2) The second stage is different. Each SoC has its own way of handling interrupts, finding interrupt numbers, and further finding the corresponding ISR addresses based on its own real-time requirements and the number of interrupt sources it supports.

4. Main registers for S5PV210 interrupt processing

1. VICnINTENABLE and VICnINTENCLEAR (n from 0 to 3) S5PV210 has designed four interrupt registers, each 32 bits

These two registers each bit corresponds to an interrupt source

(1)VICnINTENABLE 对应interrupt enable，INTENCLEAR对应interrupt enable clear

(2) The INTENABLE register is responsible for enabling the corresponding interrupt, and the INTENCLEAR register is responsible for disabling the corresponding interrupt.

(3) When we want to enable an interrupt, we only need to write 1 to the corresponding bit of VICnINTENABLE corresponding to the interrupt number (enabling means enabling the interrupt, which means that the CPU can receive the interrupt when the hardware generates an interrupt) (note that writing 1 to this bit and writing 0 to other bits will have no effect on other bits (that is, the 32 bits of this register are read and written together)); if we want to disable an interrupt source, we only need to write 1 to the corresponding bit in VICnINTENCLEAR.

Notice:

There are two designs here: some CPUs use one register bit for interrupt enable and disable, writing 1 enables and writing 0 decimal (or vice versa, writing 1 decimal and writing 0 enables). Such interrupt enable design requires great care and requires the use of the read-modify-write trilogy we mentioned earlier; the other is to separate enable and disable into two registers, writing the enable register to enable and writing the disable register to disable. The advantage of this is that we do not need to read-modify-write when enabling/disabling, and can just write directly.

2、VICnINTSELECT

This register also corresponds to an interrupt source for each bit

(1) Set the interrupt mode to irq or fiq. Generally, it is set to irq

(2)What is the difference between IRQ and FIQ?

210 supports two types of interrupts, IRQ and FIQ. IRQ is a normal interrupt, and FIQ is a fast interrupt. Fast interrupts provide an interrupt channel that responds faster and is used for interrupt sources that have high real-time requirements. FIQ provides some mechanisms in advance when the CPU is designed to ensure that FIQ can be processed quickly, thereby ensuring real-time performance. The limitation of FIQ is that only one interrupt source can be set as FIQ, and the others are IRQ.

(3)How does the CPU ensure that FIQ is faster than IRQ?

There are two reasons: first, FIQ mode has dedicated r8~r12 registers, so the r8-r12 registers can be used directly in the FIQ isr without saving, which can save time; second, FIQ is the last exception vector entry in the exception vector table. Therefore, the FIQ isr does not need to jump and can be written directly in place, which jumps one less time than other exceptions and saves some time.