ATmega16 Interrupt Vectors

This section describes the interrupt handling of the ATmega16. For more general AVR interrupt handling, see P11 “Reset and Interrupt Handling”.

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Table 19 shows the location of reset and interrupt vectors under different BOOTRST/IVSEL settings. If the program never enables interrupts, the interrupt vector is meaningless. Users can write programs directly here. Similarly, if the reset vector is located in the application area and other interrupt vectors are located in the Boot area, the program can be written directly after the reset vector. The same is true in reverse.

The typical reset and interrupt settings of ATmega16 are as follows:
Address Symbol Code Description
$000 jmp RESET; Reset interrupt vector
$002 jmp EXT_INT0; IRQ0 interrupt vector
$004 jmp EXT_INT1; IRQ1 interrupt vector
$006 jmp TIM2_COMP; Timer2 compare interrupt vector
$008 jmp TIM2_OVF; Timer2 overflow interrupt vector
$00A jmp TIM1_CAPT; Timer1 capture interrupt vector
$00C jmp TIM1_COMPA; Timer1 compare A interrupt vector
$00E jmp TIM1_COMPB; Timer1 compare B interrupt vector
$010 jmp TIM1_OVF; Timer1 overflow interrupt vector
$012 jmp TIM0_OVF; Timer0 overflow interrupt vector
$014 jmp SPI_STC; SPI Transmission end interrupt vector
$016 jmp USART_RXC ; USART RX end interrupt vector
$018 jmp USART_UDRE ; UDR empty interrupt vector
$01A jmp USART_TXC ; USART TX end interrupt vector
$01C jmp ADC ; ADC conversion end interrupt vector
$01E jmp EE_RDY ; EEPROM ready interrupt vector
$020 jmp ANA_COMP ; Analog comparator interrupt vector
$022 jmp TWSI ; Two-wire serial interface interrupt vector
$024 jmp EXT_INT2 ; IRQ2 interrupt vector
$026 jmp TIM0_COMP ; Timer 0 compare interrupt vector
$028 jmp SPM_RDY ; SPM ready interrupt vector
;
$02A RESET: ldi r16,high(RAMEND) ; Main program
$02B out SPH,r16 ; Set stack pointer to RAM $ 02C
ldi r16,low(RAMEND)
$02D out SPL,r16
$02E sei ; Enable interrupt
$02F xxx
... ... ...

When the fuse bit BOOTRST is not programmed, the Boot area is 2K bytes, and the IVSEL of the register GICR is set,
the typical reset and interrupt settings are as follows:
Address Symbol Code Description
$000 RESET: ldi r16,high(RAMEND) ; Main program
$001 out SPH,r16 ; Set the stack pointer to the top of RAM
$002 ldi r16,low(RAMEND)
$003 out SPL,r16
$004 sei ; Enable interrupt
$005 xxx
;
.org $1C02
$1C02 jmp EXT_INT0 ; IRQ0 interrupt vector
$1C04 jmp EXT_INT1 ; IRQ1 interrupt vector
... .... .. ;
$1C28 jmp SPM_RDY ; SPM ready interrupt vector
When the fuse bit BOOTRST is programmed and the Boot area is 2K bytes, the typical reset and interrupt settings are as follows:
Address Symbol Code Description.org
$002
$002 jmp EXT_INT0 ; IRQ0 interrupt vector
$004 jmp EXT_INT1 ; IRQ1 interrupt vector
... .... .. ;
$028 jmp SPM_RDY ; SPM ready interrupt vector
;
.org $1C00
$1C00 RESET: ldi r16,high(RAMEND) ; Main program
$1C01 out SPH,r16 ; Set the stack pointer to the top of RAM
$1C02 ldi r16,low(RAMEND)
$1C03 out SPL,r16
$1C04 sei ; Enable interrupt
$1C05 xxxWhen

the fuse bit BOOTRST is programmed, the Boot area is 2K bytes, and the IVSEL of the register GICR is set,
the typical reset and interrupt settings are as follows:
Address Symbol Code Description.org
$1C00
$1C00 jmp RESET ; Reset interrupt vector
$1C02 jmp EXT_INT0 ; IRQ0 interrupt vector
$1C04 jmp EXT_INT1 ; IRQ1 interrupt vector
... .... .. ;
$1C28 jmp SPM_RDY ; SPM ready interrupt vector
;
$1C2A RESET: ldi r16,high(RAMEND) ; Main program
$1C2B out SPH,r16 ; Set the stack pointer to the top of RAM
$1C2C ldi r16,low(RAMEND)
$1C2D out SPL,r16
$1C2E sei ; Enable interrupt
$1C2F xxxMove

interrupt vectors between application area and boot areaThe 

general interrupt control register determines the location of the interrupt vector tableGeneral

interrupt control register - GICR

· Bit 1 – IVSEL: Interrupt vector selection
When IVSEL is "0", the interrupt vector is located at the starting address of the Flash memory; when IVSEL is "1", the interrupt vector is transferred to the starting address of the Boot area. The actual starting address of the Boot area is determined by the fuse bit BOOTSZ. For details, please refer to P234 "Supporting Boot Loader - Self-Programming Capability that Can Be Read While Writing (RWW, Read-While-Write)". In order to prevent unintentional changes to the interrupt vector table, the following process needs to be followed when modifying IVSEL:
1. Set the interrupt vector modification enable bit IVCE
2. Write the required data to IVSEL in the next 4 clock cycles, and write "0" to IVCE
. When executing the above sequence, the interrupt is automatically disabled. In fact, the interrupt is disabled when IVCE is set, and it remains disabled until the next statement after the IVSEL write operation. If there is no IVSEL write operation, the interrupt remains disabled for 4 clock cycles after setting IVCE. It should be noted that although the interrupt is automatically disabled, the value of bit I of the status register is not affected by this operation.
Note: If the interrupt vector is located in the Boot area and the Boot lock bit BLB02 is programmed, the interrupt is disabled when the program in the application area is executed; if the interrupt vector is located in the application area and the Boot lock bit BLB12 is programmed, the interrupt is disabled when the program in the Boot area is executed. For details on the Boot lock bit, please refer to P234 "Supporting Boot Loader -
Read-While-Write Self-Programming Capability".

· Bit 0 - IVCE: Interrupt Vector Modification
Enable IVCE must be set when changing IVSEL. IVCE is cleared by hardware 4 clock cycles after the IVCE or IVSEL write operation. As mentioned earlier, setting IVCE will disable interrupts. The code is as follows:

Assembly code routine:
Move_interrupts:
; Enable modification of interrupt vector
ldi r16, (1<out GICR, r16
; Transfer interrupt vector to boot area
ldi r16, (1<out GICR, r16
ret
C code routine
void Move_interrupts(void)
{
/* Enable modification of interrupt vector*/
GICR = (1</* Transfer interrupt vector to boot area*/
GICR = (1<}