Summary of issues related to PC, LR, SPSR, and CPSR registers when an ARM interrupt occurs

Q: How is the context saved when ARM enters IRQ interrupt from SVC mode?

Answer: When saving the scene, when in svc mode, the cpsr register is written to the spsr_irq register in irq mode, not the spsr_svc in svc mode. In this way, if you restore in interrupt mode, write the content of the spsr_irq register to the cpsr, and you can restore to svc mode, because the content of the spsr_irq register is the state in svc mode.

In addition, the PC pointer address will be assigned to the LR register when an interrupt occurs, but the assignment object is not the LR_svc register, but the LR_irq register in IRQ mode.

Therefore, after entering the interrupt IRQ mode, the SPSR and LR registers must be pushed into the stack as soon as possible, and then popped when needed to return.

Q: When will the LR register be assigned a value?

A: There are two situations. One is that when an interrupt exception occurs, LR will be assigned a value, as described above. The other is when a function call occurs, using the BLX and BL instructions, which will cause the LR register to be assigned a return address.

Question: When switching modes by manually changing the last few bits of the CPSR register, will hardware assignment occur?

A: No, after manually switching the mode, the mapping addresses of the corresponding registers such as LR and spsr will change, and the registers accessed are not in the same location, but no hardware assignment will occur. The mode switch does not affect the code, and the code will continue to run where it should.

Question: When the program returns, why is it only necessary to assign the PC address? Why is there no instruction to assign the SPSR to the CPSR?

Answer: Regarding restoring the original value of CPSR:

If the instruction has an S suffix (except for comparison instructions) and the PC is used as the target register for the operation,

In abnormal mode: the CPSR is restored from the SPSR while the operation is in progress. For example:

movs pc, #0xff /* cpsr = spsr; pc = 0xff /

adds pc, r1, #0xffffff00

/cpsr = spsr; pc = r1 + 0xffffff00 /

ands pc, r1, r2 / cpsr = spsr; pc = r1 & r2; */

In user or system mode: Unpredictable results may occur because there is no SPSR in these two modes.

Popular explanation: This is to achieve switching between modes, because, if you want to switch from other modes to user mode, you must use an instruction to do so. If you cannot use an instruction to do so, problems will arise. For example, copy spsr to cpsr first. Once this instruction is completed, the mode will switch. At this time, LR does not store the target address to be jumped to, because the mode has changed, and the mapping of LR has changed. Similarly, if LR is copied to PC first, when the next clock beat arrives, the CPU will execute the content pointed to by PC, and the program to restore SPSR will not be executed.