Analysis of the misaligned connection between Memory Controller and peripheral address lines of s3c2440

As shown in the s3c2440 data sheet:

When the data bit width of the peripheral Flash is 8 bits, (the address line of the Memory Cotroller) A0——A0 (A0 of the peripheral Flash);

When the data bit width of the peripheral Flash is 16 bits, (the address line of the Memory Cotroller) A1——A0 (A0 of the peripheral Flash);

When the data bit width of the peripheral Flash is 32 bits, (the address line of the Memory Cotroller) A2——A0 (A0 of the peripheral Flash);

reason:

The smallest data unit corresponding to the CPU address line (LADDR0~LADDR20) is byte, that is, 8 bits;

In actual applications, the peripheral Flash used usually has a data bit width of 8 bits, 16 bits, and 32 bits. The CPU must accurately obtain data according to the 8-bit data bit width. There must be an intermediate layer between the CPU and the Flash to solve this problem, which is the Memory Controller.

According to the data bit width of the peripheral Flash, through hardware processing, read 8-bit data processing method according to each address. For example, the data bit width of NOR Flash is 16 bits, as shown in the figure:

1. Read data from Nor flash

1. Get 1 byte of data each time

a. When the CPU wants to obtain the data at address 0, the Memery Controller sends the address 0b000000000000000000000, the NOR Flash receives the address 0b000000000000000000000, and returns the first data on the data line (LDATA0~LDATA15) to the Memery Controller of the CPU. The Memery Controller selects the lower 8 bits and gives them to the CPU.

b. When the CPU wants to obtain the data at address 1, the Memery Controller sends the address 0b000000000000000000001. The NOR Flash receives the address 0b0000000000000000000000 and returns the first data on the data line (LDATA0~LDATA15) to the Memery Controller of the CPU. The Memery Controller selects the upper 8 bits and gives them to the CPU.

2. Get 2 bytes of data each time

When the CPU wants to obtain the data at address 0, 1, the Memery Controller sends the address 0b000000000000000000000, the NOR Flash receives the address 0b000000000000000000000, and returns the first data on the data line (LDATA0~LDATA15) to the Memery Controller of the CPU, and the Memery Controller selects this data to the CPU.

3. Get 4 bytes of data each time

When the CPU wants to get the data at address 0, 1, 2, 3:

a. The Memory Controller sends the address 0b000000000000000000000, and the NOR Flash receives the address 0b000000000000000000000, and returns the first data on the data line (LDATA0 ~ LDATA15) to the Memory Controller of the CPU, and the Memory Controller reads this data.

b. The Memory Controller sends the address 0b000000000000000000010. The NOR Flash receives the address 0b000000000000000000001 and returns the second data on the data line (LDATA0 ~ LDATA15) to the Memory Controller of the CPU. The Memory Controller reads this data and combines the two 16-bit data into a 32-bit data and returns it to the CPU.

2. Write data to NOR Flash

1. Write 1 byte of data each time

a. When the CPU wants to write data to address 0, the Memery Controller sends the address 0b000000000000000000000, the NOR Flash receives the address 0b000000000000000000000, the CPU transmits the 8-bit data to the Memery Controller, and the Memery Controller sends the data to the lower 8 bits of the NOR Flash data line (LDATA0~LDATA7).

b. When the CPU wants to write data to address 1, the Memery Controller sends the address 0b000000000000000000001, the NOR Flash receives the address 0b000000000000000000000, the CPU transmits the 8-bit data to the Memery Controller, and the Memery Controller sends the data to the high 8 bits of the NOR Flash data line (LDATA8~LDATA15).

2. Write 2 bytes of data each time

When the CPU wants to write data to address 0,1, the Memery Controller sends the address 0b000000000000000000000, the NOR Flash receives the address 0b000000000000000000000, the CPU transmits the 16-bit data to the Memery Controller, and the Memery Controller sends the data to the NOR Flash data lines (LDATA0~LDATA15).

2. Write 4 bytes of data each time

When the CPU wants to write data to address 0, 1, 2, 3:

a. The Memery Controller sends the address 0b000000000000000000000, and the NOR Flash receives the address 0b0000000000000000000000. The CPU transmits the 32-bit data to the Memery Controller, and the Memery Controller sends the lower 16 bits of the data to the NOR Flash data lines (LDATA0~LDATA15).

b. The Memery Controller sends the address 0b000000000000000000010. The NOR Flash receives the address 0b000000000000000000001. The Memery Controller sends the high 16 bits of data to the NOR Flash data lines (LDATA0~LDATA15).

Summarize:

1. When the peripheral data width is 8 bits, the CPU's LADDR0-LADDRx is directly connected to the peripheral's LDATA0-LDATAx;

2. When the peripheral data width is 16 bits, the CPU's LADDR1-LADDRx is directly connected to the peripheral's LDATA0-LDATAx. Regardless of whether the CPU's LADDR0 is 0 or 1, the address obtained by the peripheral is LADDR1-LADDRx, corresponding to the same 16-bit data. The Memory Controller selects or combines this data.

3. When the peripheral data width is 32 bits, the CPU's LADDR2-LADDRx is directly connected to the peripheral's LDATA0-LDATAx. When the CPU's LADDR0 and LADDR0 are 00, 01, 10, or 11, the addresses obtained by the peripheral are all LADDR2-LADDRx, corresponding to 32-bit data. The Memery Controller selects or combines this data.