1.7.3_NandFlash chip ID reading

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The timing diagram of read ID found in the nand flash chip manual is as follows.
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Let's analyze this timing diagram.

Generally, we first operate the chip select, which means selecting the chip. Through the 2440 chip manual, we write the following two functions for subsequent calls.
insert image description here Next, we have the write enable pin and command latch pin. As we have analyzed in the previous section, the operation interval between them is 0ns, which means they can be operated directly. After that, we issue the command 0x90 to read the ID. The operation of the write enable and command latch pins will be operated by the nand flash controller of 2440. We only need to write the command to NFCMD.

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For subsequent operations, we only need to read data from NFDATA and write addresses to NFADDR. The complicated and tedious timing operations will be performed by the nand flash controller for us.

In addition, print out the block information and page information of the nand flash, which are obtained through the 4th code.
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It should be noted that since the program exceeds 4K, if the program's nand boot has not been done, it should be started from nor first.

Keywords：NandFlash Reference address：1.7.3_NandFlash chip ID reading_P

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