6. Learn ARM from scratch - exception and interrupt handling, exception vector table, swi

1. Exception

Exception is the most important knowledge point to understand the operation of CPU. Almost every processor supports specific exception handling, and interrupt is one of the exceptions.
Sometimes when we measure the real-time performance of an operating system, we look at the shortest interrupt response time of the OS and the number of interrupt responses per unit time.

2. Abnormal Source

In the ARM architecture, there are 7 types of exception handling. When an exception occurs, the processor sets the PC to a specific memory address. This address is placed in a specific address range called a vector table. The entry of the vector table is some jump instructions that jump to a subroutine that specifically handles a certain exception or interrupt.

1. Abnormal source classification

To enter the exception mode, there must be an exception source. ARM stipulates 7 exception sources:

1. reset abnormal

This exception is entered when the CPU is just powered on or after the reset button is pressed. This exception is handled in management mode.

1. irq/fiq general/fast interrupt request

The CPU and external devices are independent hardware execution units. The CPU manages all devices and schedules resources. If the CPU wants to know the operating status of external devices, it either checks the specific registers of the external devices at regular intervals, or allows the external devices to "interrupt" the CPU when CPU intervention is required, so that it can handle the requests of the external devices. There is no doubt that the second method is more reasonable, allowing the CPU to "concentrate" on its work. The "interrupt" operation here is called an interrupt request. According to the urgency of the request, interrupt requests are divided into general interrupts and fast interrupts. Fast interrupts have the highest interrupt priority and the smallest interrupt delay. They are usually used to process high-speed data transmission and channel data recovery processing, such as DMA. Most peripherals use general interrupt requests.

1. Prefetch instruction abort exception

This exception occurs in the instruction fetch stage of the CPU pipeline. If the target instruction address is an illegal address, the exception is entered and the exception is handled in the abort exception mode.

1. Undefined instruction exception

This exception occurs in the decoding stage of the pipeline technology. If the current instruction cannot be recognized as a valid instruction, an undefined instruction exception is generated. This exception is handled in the undefined exception mode.

1. Software interrupt instruction (swi) exception

This exception is generated when the application calls itself, and is used when the user program requests access to hardware resources, for example: printf() printing function, to print user data to the display, the user program must apply to use the display to achieve printing, and the user program does not have the right to use the peripheral hardware, and can only switch to the kernel state by using the software interrupt instruction, and access the peripheral hardware through the operating system kernel code. The kernel state works in privileged mode, and the operating system completes the printing of user data to the display in privileged mode. The purpose of doing this is nothing more than to protect the security of the operating system and the rational use of hardware resources. This exception is handled in management mode.

1. Data abort access exception
   This exception occurs when the data address to be accessed does not exist or is an illegal address. This exception is handled in abort exception mode.

2. ARM exception priority

Reset→

Data abort→

FIQ→

IRQ→

Prefetch abort→

Undefined instruction/SWI.

3. Why FIQ is faster than IRQ

1. fiq has higher priority than irq

2. The FIQ vector is at the end of the vector table, and exception handling does not require a jump

3. FIQ has 5 more private registers (r8-r12) than IRQ, and fewer stack push and pop operations are performed during interrupt operations.

3. Hardware Operations That Occur Abnormally

After an exception occurs, the operation steps of the ARM core can be summarized into 4 big steps and 3 small steps.

1. 4 big steps and 3 small steps

1. Save execution state: copy CPSR to SPSR in the exception mode that occurred;

2. Mode switch:

• The CPSR mode bits are forced to the value corresponding to the exception type,

• The processor enters ARM execution mode.

• Disable all IRQ interrupts, and disable FIQ interrupts when entering FIQ fast interrupt mode;

1. Save the return address: Save the address of the next instruction (interrupted program) in LR (LR_excep in exception mode).

2. Jump into the exception vector table: force the PC value to be set to the corresponding exception vector address and jump to the exception handler.

2. Detailed steps

1. Save execution status

The execution status of the current program is saved in the CPSR. When an exception occurs, the execution status in the current CPSR is saved in the SPSR in the exception mode. When the exception returns in the future, the CPSR is restored to the execution status.

1. Mode Switching

The hardware automatically writes the exception code to the M[4:0] mode bit in the CPSR according to the current exception type, so that the CPU enters the corresponding exception mode. Regardless of whether an exception occurs in the ARM state or the THUMB state, it will automatically switch to the ARM state for exception processing. This is done automatically by the hardware, setting CPSR[5] to 0. At the same time, the CPU will turn off the interrupt IRQ (set the I bit of the CPSR register) to prevent interrupts from entering. If the current exception is a fast interrupt FIQ, turn off the fast interrupt (set the F bit of the CPSR register).

1. Save return address

The current program is interrupted by an exception and switches to the exception handler. After the exception is handled, it returns to the current interrupted mode to continue execution. Therefore, the address of the next instruction of the currently executed instruction must be saved to LR_excep (LR in exception mode, there is no LR_excep register, _excep is added for the convenience of readers to understand, the same principle applies below). Due to different exception modes and the use of pipeline technology in the ARM core, the exception handler must calculate the return address according to the exception mode.

1. Jump into the exception vector table

This operation is automatically performed by the CPU hardware. When an exception occurs, the CPU forces the value of PC to be modified to a fixed memory address. This fixed address is called the exception vector.

4. Exception Vector Table

The exception vector table is a specific memory address space. Each ARM exception corresponds to a word length space (4Bytes), which is exactly the length of a 32-bit instruction. When an exception occurs, the CPU forces the value of PC to be set to the fixed memory address corresponding to the current exception.

1. Exception vector table:

The operation of jumping into the exception vector table is automatically completed by the hardware when an exception occurs, and the remaining exception handling tasks are completely handed over to the programmer. As can be seen from the above table, the exception vector is a fixed memory address. We can complete the exception handling by writing a jump instruction to this address and letting it jump to the entry of the exception handler we define ourselves.

It is because of the existence of the exception vector table that the hardware exception handling and the programmer's custom handler are organically linked. The address 0x00000000 in the exception vector table is the reset exception. The reason why it is address 0 is because the CPU automatically loads instructions from address 0 when it is powered on. It can be seen that installing the reset exception at this address is also designed to be connected before and after. I have to sigh at the greatness of the CPU designer. Behind it are the other 7 exception vectors. Each exception vector occupies four bytes, which is exactly the size of an instruction. The last exception is the fast interrupt exception. Installing it here also has its significance. The fast interrupt handler can be directly stored at the address 0x0000001C without setting a jump instruction. This can save a clock cycle and speed up the fast interrupt processing time.

The memory mapping address 0x00000000 is reserved for the vector table. In some processors, the vector table can be located at the high address 0xFFFF0000 [configurable through coprocessor instructions]. In order to control memory access rights, today's operating systems usually enable virtual memory. After enabling virtual memory, the starting space of the memory is usually the kernel process space and the page table space. The exception vector table can no longer be installed at address 0.

For example, the Cortex-A8 system supports placing the first address of the exception vector table at any address by setting the C12 register of CP15.

2. Install the exception vector table

We can install the exception vector table by simply using the following command:

b reset ; jump into the reset handler

b HandleUndef ; jump into the undefined handler

b HandSWI ; Jump into the soft interrupt handler

b HandPrefetchAbt ; Jump into the prefetch instruction handler

b HandDataAbt ; Jump into the data access abort handler

b HandNoUsed ; Jump into unused program

b HandleIRQ ; Jump into interrupt handler

b HandleFIQ ; Jump into the fast interrupt handler