Detailed explanation of 51 MCU registers

Special function registers of 51 microcontroller

Timer:

Timing mode register TMOD (address 89H);

TMOD is divided into two parts, each with 4 bits, which are used to control T1 and T0 respectively.

GATE

C/T

M1

M0

GATE

C/T

M1

M0

1. M1, M0: working mode of timer/counter

1. Working mode 0: 13-bit timing/counting mode (8192).

2. Working mode 1: 16-bit timing/counting mode (65536).

3. Working mode 2 and working mode 3, 8-bit timing/counting mode (256).

2. If C/T is 0, it is used as a timer. If C/T is 1, it is used as a counter.

3. Gate bit GATE (GATE=0 has nothing to do with INT0, GATE=1 has something to do with INT0):

1. GATE=0, whether the timing/counting works depends only on TR1.

2. GATE=1, it is not only controlled by TR1, but also by INT1 pin. Only when TR1 is 1 and INT1 pin is also high level, the counting pulse can pass.

Timer/Counter Control Register TCON (Address 88H):

Timer/Counter

External interrupt

TF1

TR1

TF0

TRO

IE1

IT1

IE0

IT0

TF1/TF0 - Timer/Event Counter overflow flag.

TR1/TR0 - Timer/Event Counter Run Control Bit. When set, the timer/event counter starts running.

IE1/IE0 - External interrupt (INTx) flag. IE1/IE0 = 1 means there is an interrupt on INTx; IE1/IE0 = 0 means hardware reset.

IT1/IT0 - External interrupt trigger type control bit. When IT1/IT0=1, it is a falling edge trigger interrupt; when IT1/IT0=0, it is a low level trigger interrupt.

Interrupt system:

Interrupt Enable Register IE

EA

X

ET2

ES

ET1

EX1

ET0

EX0

EA - interrupt master switch, if it is equal to 0, all interrupts are not allowed.

ES - Serial Port Interrupt Enable

ET1-Timer 1 interrupt enable

EX1-External interrupt 1 interrupt enable

ET2-Timer 2 interrupt enable

ET0-Timer 0 interrupt enable

EX0-External interrupt 0 interrupt enable

Interrupt priority control register IP

X

X

PT2

PS

PT1

PX1

PT0

PX0

PT2-T2 interrupt priority control

PS - Serial port interrupt priority control

PT1-T1 interrupt priority control

PX1-INT1 interrupt priority control

PT0-T0 interrupt priority control

PX0-INT0 interrupt priority control

Serial Communication:

Serial port control register SCON (address is 98H)

SM0

SM1

SM

REN

TB8

RB8

TI

RI

SM0, SM1: Serial port working mode selection bits, which are defined as follows:

SM0, SM1

Way of working

Functional Description

Baud rate

0

0

Method 0

8-bit shift register

Fosc/12

0

1

Method 1

10-bit UART

variable

1

0

Method 2

11-bit UART

Fosc/64 or fosc/32

1

1

Method 3

11-bit UART

variable

Where fosc is the crystal frequency

SM2: Multi-machine communication control bit. In mode 0, SM2 must be equal to 0. In mode 1, when (SM2) = 1, RI is set to 1 only when a valid stop bit is received. In mode 2 or mode 3, when (SM2) = 1 and the received ninth bit of data RB8 = 0, RI is set to 1.

REN: Receive enable control bit. It is set by software to enable reception and cleared by software to disable reception.

TB8: is the 9th bit of the data to be sent. In mode 2 or mode 3, the 9th bit of data to be sent is set to 1 or cleared to 0 by software as needed. For example, it can be agreed to be used as a parity bit, or as a flag bit to distinguish address frames or data frames in multi-machine communication.

RB8: The 9th bit of the received data. RB8 is not used in mode 0. In mode 1, if (SM2) = 0, RB8 is the received stop bit. In mode 2 or mode 3, RB8 is the 9th bit of the received data.

TI: Transmit interrupt flag. In mode 0, it is set by hardware when the 8th bit is sent. In other modes, it is set by hardware before the send stop bit. TI setting indicates that a frame of information has been sent, and it also requests an interrupt. You can use software query methods to obtain information that data has been sent, or use interrupts to send the next data as needed. TI must be cleared to 0 by software.

RI: Receive interrupt flag. In mode 0, it is set by hardware after receiving the 8th bit of data. In other modes, it is set by hardware at the middle of receiving the stop bit (see the description of SM2 for exceptions). RI is set to indicate that a frame of data has been received, which can be obtained by query or interrupt. RI must also be cleared to 0 by software

Power Control Register PCON

SMOD

X

X

X

GF1

GF0

PD

IDL

SMOD - Baud rate selection bit. When SMOD = 1, the baud rate of modes 1, 2 and 3 is doubled.

GF1/GF0 - General purpose flags

PD - Power-down control bit. 1: Power-down mode 0: Normal mode

IDL - Idle control bit. 1: Idle mode 0: Normal mode