ARM11 learning based on S3C6410 (XV) MMU is here

Now, we have come to the world of main. Next, we will experience the MMU of ARM11, which is not available in STM32. Previously, during the core initialization process, the MMU function was turned off. That is because at that time, the operations were all physical addresses, so the MMU needed to be turned off.

 MMU, memory management unit. It has two main functions:

1. Convert virtual address to physical address

2. Memory access rights management

The figure above illustrates the role of MMU.

There are three tasks running, and the running address is 0x400000. If it is not processed, it will definitely not work. So MMU is added. MMU is actually a page table. The virtual address is mapped to the physical address by looking up the table. Although the running address of the three tasks is 0x400000, this address is a virtual address. In the page table, the virtual address of each task is mapped to a different physical address. In this way, each task can be implemented at the same virtual address but run at different physical addresses.

So to use MMU, we must first create this page table. Who creates this page table? We create it ourselves. Create a page table of physical memory corresponding to virtual memory, so that MMU can find the physical address corresponding to the virtual address from the page table.

MMU has primary and secondary translation, which is actually looking up the table several times. For primary translation, the physical address is determined by looking up the page table only once. In S3C6410, the method is segment mapping. For secondary translation, the page table must be checked twice or three times to determine the physical address. This is in S3C6410. There are two methods, a fine page method and a coarse page method. The difference between these two methods is that the size of each page is different.

The above figure is a first-level translation descriptor. Through the virtual address [31:20], find the corresponding translation descriptor, which is actually a 32-bit data stored in RAM. By judging the last two bits of this descriptor, determine what kind of conversion it is. If it is a segment conversion, convert the physical address according to the format of the segment conversion. If it is a page conversion, find the second-level page table, and then convert the physical address according to the format of the second-level page table.

First, look at the segment translation of the next level translation page table.

The first-level page table always contains 4096 translation descriptors. Because it is addressed by bits 31:20 of the virtual address. The maximum number that can be represented by 12 bits is 4096, so the first-level page table has a total of 4096 translation descriptors. The first address of the page table is TTB, which is very important because only with this address can we know where the page table is located and find the corresponding descriptor through the offset. Therefore, there is a register to save this address, which is the c2 register of CP15.

By using the high 12 bits of the virtual address offset, we find the corresponding descriptor in the page table and determine the last two bits of the descriptor to determine what the conversion is. If it is 10, it means it is a segment conversion.

After determining that it is a segment conversion, the upper 12 bits of the descriptor are taken out. This is the physical base address. When it is concatenated with the last 20 bits of the virtual address, the corresponding physical address is obtained.

For segment conversion, each segment represents a physical 1MB address. Why is it 1MB? Because there are 4096 descriptors in total, and ARM11 is 32 bits, so the space that can be represented is 4G. In this way, each segment represents 1MB of space.

The principle of secondary conversion is the same. It just requires more table lookups. Here is a rough diagram of the conversion of a fine page.

It is to get the physical address by continuously looking up the table.

The current learning is based on segment conversion, so let's talk about segment conversion. Let's first look at the first-level page table descriptor.

The last two digits indicate what the conversion is. 10 is a segment conversion.

B: Indicates whether the write buffer is enabled

C: Indicates whether cache is enabled

XN：

Domain: It is used to indicate which domain the segment belongs to. ARM11 has 16 domains, and each domain can have different permissions. When a segment is assigned to a domain, the permissions of the segment are the same as the permissions of the domain.

P: Indicates that the segment has ECC, which is not supported by ARM11, so this bit is 0.

AP: Access permission. This domain specifies the access permission for this address segment.

TEX: The function of this is not very clear at present.

APX: Provides additional access rights.

S: Indicates whether the region is shared. 0 means not shared, 1 means shared. The manual says that this is for multi-core use. It is not used at present, so set it to 0.

nG:

NS:

Section base address: This is the upper 12 bits of the segment's physical address.

The following figure shows the access permissions

In order to make the space readable and writable, the values ​​of APX and AP[1:0] are set to 011.

The access rights set here must also be coordinated with the domains set. ARM11 supports 16 domains, which are set by C3 of CP15. On page 195 of the ARM11 core manual, it is stated:

Each two bits of the register correspond to an area. Different values ​​will have different access permissions. If it is set to 00 or 10, an exception will occur when accessing. If it is 01, the permissions set in the MMU need to be checked. If it is set to 11, no access permission is checked. All are considered accessible.

For simplicity, all are set to 11. So the value of this register is 0xffffffff.

The next step is to design the program.

The first step is to create a page table. If segment mapping is used, the segment mapping descriptor must be written to the corresponding memory.

First, put the page table in the first position of ddr, which is 0x50000000. So this address needs to be written into TTB.

This time, the light flashing is realized through the virtual address, so it is necessary to establish a mapping from the virtual address to the physical address of the GPIO register.

Secondly, after turning on the MMU, the virtual address is used, so the page table of the program segment must be established. Otherwise, once the MMU is turned on, the CPU will send out the virtual address when fetching instructions, but there is no mapping table from virtual address to physical address. In this case, the instruction cannot be fetched and the program crashes. Therefore, it is necessary to establish a mapping page table for the code area. The mapping of the code area is to directly convert the virtual address into the physical address for use.

First determine the two register addresses of GPIO

Just change the value of the first 8 bits. Next, map this address to the 0x7F000000 area.

The code is also relatively simple. First, declare a ttb pointer, which points to the base address of the first-level table, that is, the first address of ddr, 0x50000000. Then declare two variables, one for the virtual address and the other for the physical address.

According to the previous first-level segment descriptor format, you can write data to the corresponding memory unit. The upper 12 bits of the segment descriptor are the upper 12 bits of the physical address, so first there is an operation of ANDing the physical address and 0xFFF00000 to write the upper 12 bits of the physical address into the segment descriptor.

The following bits can be configured accordingly. Take a look at this defined macro.

Set the access permission to 11, that is, no access permission check is performed. Set the domain to 0. Turn off both the cache and write buffer. Because this is just an operation on a register, there is no need to use the cache and write buffer.

If macro definitions are used here, the readability of the program will be much better. Of course, you can also assign values ​​to this descriptor directly without using this macro definition method, but this will make the program less readable because you have to check the manual to know what the value you assign is used for.

Here, *(ttb + (vaddr >> 20)) is used to assign the corresponding page descriptor. In the first-level page table, the offset is determined by the upper 12 bits of the virtual address. The upper 12 bits are 20 bits, so here the value of the virtual address shifted 20 bits right is added, that is, the value of the upper 12 bits is taken out. Note that this is a pointer operation. Assuming that the upper 12 bits of the virtual address are 5 at this time, the address written is not 0x50000005, but 0x50000014. Because the data type of the pointer is long, 4 bytes, if 1 is added, the address will be increased by 4, and if 5 is added, the address will be increased by 5*4=20.

In this way, the GPIO page table is established. Accessing the virtual address 0xc7000000 means accessing the physical address 0x7f000000. The entire segment space is 1Mb.

Next, we need to create a page table for the code area.

At this time, the code is already running in the memory, so all the address spaces of the memory are directly mapped, and the space is 64MB.

The macros used here

In fact, it is just one more thing to open CACHE and WRITE BUFFER.

Memory mapping is to map an area, from 0x50000000 to 0x54000000, which is a 64M virtual address, to 0x50000000 to 0x54000000, which is a 64M physical address. In this way, even if you use the virtual address to get the data in the ddr, you can get it.

Because a segment is a 1MB space, a total of 64 segments are needed, which is 0x40 in hexadecimal. Therefore, in the while statement, the virtual address must be less than 0x54000000. Furthermore, each segment represents 1MB of space, so both the virtual address and the physical address must be added by 1MB, which is 0x100000.