Arm system architecture knowledge summary

Mainboard——Core board + expansion circuit + interface

Core board——cpu+peripheral circuit+interface

ARM architecture knowledge points:

Core (kernel) programming method

Interface (Peripheral Module) Technology

Chip price: Moore's Law, chip price doubles every 18 months. After 18 months, the price drops by half.

Now chip circuits: designed using hardware description language.

Chip manufacturer: buy the hardware description language programming kernel of ARM's chip, plus some peripheral modules.

The core is unified, but each part of the periphery is fighting on its own.

arm：Advanced RISC Machines

ARM company website: http://www.arm.com

ARM is not only a company but also a general term for a type of microprocessor. Chips based on ARM core are collectively called ARM chips.

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Arm Architecture

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ARM architecture features:

ARM instructions are all 32-bit fixed-length;

A large number of registers (37 registers);

Load/Store architecture;

Load/Store instructions for multiple registers;

Conditional execution of instructions;

Complete data shift operations and ALU operations in a single instruction executed in a single clock cycle;

Extending the capabilities of ARM processors through variants and co-processors;

The 16-bit Thumb instructions are extended to improve code density.

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Naming of arm series:

ARM1 Series:

Architecture: ARMv1 (Core ARM1)

ARM2 Series:

Architecture: ARMv2 (Core ARM2)

ARMv2a series:

Architecture: ARM250

ARM3 Series:

Architecture: ARMv2a (Core ARM2a)

ARM6 series:

Architecture: ARMv3 (Core ARM610)

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ARM7TDMI series: three-stage pipeline

Architecture: ARMv4T

ARM9TDMI series: five-stage pipeline

Architecture: ARMv4T

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ARM9E Series:

Architecture: ARMv5

ARM10E series: six-stage pipeline

Architecture: ARMv5

XScale Series:

Architecture: ARMv5TE

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ARM11 series: eight-stage pipeline

Architecture: ARMv6 (Core: ARM1136J(F)-S);

Architecture: ARMv6T2 (Core: ARM1156T2(F)-S);

Architecture: ARMv6KZ (Core: ARM1176JZ(F)-S);

Architecture: ARMv6K (Core: ARM11MPCore);

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Cortex series: 13-stage pipeline

Architecture: ARMv7-A (Application) (Core: Cortex-A8): Application processor for complex operating systems and user applications.

Architecture: ARMv7-R (Real-time) (Core: Cortex-R4 (F)): Embedded processor suitable for real-time systems.

Architecture: ARMv7-M (Microcontroller) (Core: Cortex-M3): Designed for cost- and power-sensitive embedded applications, the goal is to achieve 32-bit high performance at the price of an 8-bit microcontroller.

Variants for the arm architecture:

Thumb instruction set (T variant): instruction length is 16 bits.

Long multiplication instructions (M variant):

Enhanced DSP instructions (E variant):

Java accelerator Jazelle (J variant):

ARM processor naming format:

ARM x y z T D M I E J F -S

x : sequence

y: 2: with MMU, 4 with MPU, 6 without

z: 0: standard cache, 2: reduced cache, 6: variable cache

T: The processor supports the Thumb instruction set

D: Support JTAG debugger

M: Support long multiplication instructions

I: With embedded trace macrocell

E: Support enhanced instructions (based on TDMI)

J: Support JAVA hardware acceleration (Jazelle)

F: Support vector floating point unit

S: Synthesizable version

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arm instruction pipeline:

Fetch: The instruction fetch unit of the microprocessor obtains the instruction to be executed from the memory and stores it in the instruction register.

Decode: Analyze the instructions in the instruction register to determine what operation to perform.

Execute: Execute the operation specified by the instruction and save the operation result as required by the instruction.

Von Neumann architecture: The instruction memory address and data memory address point to different physical locations of the same memory. Therefore, instructions and data use the same data bus, and only instructions or data can be fetched at the same time.

Harvard architecture: The instruction bus and data bus are separate and can be accessed simultaneously, and their widths can be different.

Three-stage pipeline: fetch decode execute

Five-stage pipeline: fetch decode execute memory write

The pipeline stages of the five-stage pipeline are:

Fetch

Decode

execute

Buffer/data: Accesses data memory if necessary, otherwise the ALU simply buffers for one clock cycle so that all instructions have the same pipeline flow.

Write-back: Write the results of an instruction back to the register file, including any data read from the registers.

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Arm storage system

There are two ways of storage in ARM: big endian and little endian.

Big-endian format: The least significant byte of a word is stored at a high memory address.

Little-endian: The least significant byte of a word is stored at the lowest address in memory.

The arm default mode is little endian.

Note: The storage format of data and code in the memory must be consistent with the format used by the processor.

Arm memory hierarchy:

Register group;

On-chip RAM;

On-chip cache;

Main memory.

The storage management strategies that can be used in the arm architecture include:

Multiple types of storage units;

cache；

Write cache;

Virtual memory address.

Methods for implementing storage system management:

Enable cache to speed up memory access;

Start mapping virtual addresses to physical addresses;

Use the "domain management" policy to protect access to storage units;

Restrict access to I/O mapped address space;

Coprocessor cp15.

The ARM microprocessor has 37 32-bit registers.

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ARM chip selection

Factors related to chip performance and integration:

Whether there is an MMU;

Chip efficiency;

Internal memory capacity;

USB interface;

Number of GPIOs;

Interrupt controller;

IIS（Integrate Interface of Sound）；

nWAIT signal;

RTC(Real Time Clock);

LCD controller;

PWM output;

ADC/DAC；

Expansion bus;

UART and IrDA;

Multi-core considerations (ARM+DSP) (ARM+ARM);

Built-in FPGA;

Clock counter and watchdog;

Power management;

DMA controller;

Chip stability;

The chip supplier's technical support capabilities;

The stability of chip supply and the convenience of purchasing;

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ARM programming model (kernel programming)

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Data types of arm:

ARM supports the following three data types:

Byte: 8 bits

Half word: 16 bits

Word: 32 bits

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Working mode of arm:

Arm has seven working modes:

Two normal modes:

User mode: Normal program execution mode. Most programs are executed in this mode.

System mode: A privileged mode that uses the same register set as User mode.

Five abnormal modes:

Fast interrupt mode (FIQ): This mode is entered when a high priority (fast) interrupt occurs.

External interrupt mode (IRQ): This mode is entered when a low priority (normal) interrupt occurs.

Supervisor mode: This mode is entered when a reset or soft interrupt (SWI) instruction is executed.

Data access termination mode (Abort): This mode is entered when access is abnormal and is used for virtual storage or storage protection.

Undef mode: This mode is entered when an undefined instruction is executed, and is sometimes used to emulate the working mode of the coprocessor hardware through software.

A non-privileged mode:

User mode

Six privilege modes:

System

Fast Interrupt Mode (FIQ)

External Interrupt Mode (IRQ)

Supervisor Mode

Data access termination mode (Abort)

Undefined mode (Undef)

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Arm running status

The arm processor has two working states:

ARM state: arm state executes arm instructions, and the pc value is word aligned (32 bits).

Thumb state: Thumb instructions are executed in thumb state, and the pc value is half-word aligned (16 bits).

Switching of working status:

Use command switch

BX Rm

Rm[0] = 0 ARM state

Rm[0] = 1 Thumb state

Processor automatic switching

The processor performs exception handling. If it is in Thumb state, it enters ARM state. After the exception handling returns, it enters Thumb state.

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arm register

The ARM processor has 37 registers that are 32 bits long;

31 general registers (16 public + 15 private);

6 status registers;

The registers that can be accessed in different modes are different.

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General register: Participates in calculations or stores the results of calculations.

There are 16 common registers as follows:

usr/system: R0——R12, R13, R14, R15. (There are 16 common registers in user mode and system mode).

There are general registers with special purposes (in addition to being general registers, they also have the following functions):

R13: Stack pointer register SP.

R14: Link register LR. Generally used to indicate the exit of a program.

R15: Program counter PC, always points to the instruction address of the instruction fetch. Generally used to indicate the entry of the program.

There are 15 private registers:

irq: R0...R12, R15. (External interrupt mode has two private registers)

R13_race

R14_race

svc: R0...R12, R15. (Supervisory mode has two private registers)

R13_svc

R14_svc

abt: R0...R12, R15. (Data access termination mode has two private registers)

R13_abt

R14_abt

und: R0...R12, R15. (Undefined mode has two private registers)

R13_and

R14_and

fiq: R0-R7, R15. (Fast interrupt mode has seven private registers)

R8_fiq

R9_fiq

R10_fiq

R11_fiq

R12_fiq

R13_fig

R14_fig

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Status register psr:

one:

cpsr: Current Program Status Register (accessible in all seven modes).

Five:

spsr: Save program status register. (Only accessible in corresponding mode).

spsr_irq

spsr_svc

spsr_fiq

spsr_abt

spsr_and

cpsr/spsr register format:

Condition code identifier

31 30 29 28 7 6 5 4-0

N Z C V I F T mode