Quickly learn Arm (21)--Interrupt vector VIC controller VIC [3]

It's called fast learning, but it's not that fast. It's not easy to learn this quickly.

There are many interrupt sources that may cause interrupts. For 2400, there are probably the following interrupt sources

   Interrupt source VIC channel number

   WDT 0

   --Reserved for software interrupt 1

    ARM Core                     2

    ARM Core                     3

   TIMER0                       4

   HOUR1 5

    UART0                        6

   UART1 7

   PWM0, PWM1 8

    I2C0                         9

    SPI,SSP0                     10

    SSP1 11

    PLL                           12

    RTC                          13

    System control (external interrupt) 14,15,16,17

   ADC0                         18

   I2C1                         19

   THAT 20

   Ethernet                      21

   USB                          22

   CAN                          23

   SD/MMC                       24

    GP DMA                       25

    Timer 2                      26

    Timer 3                      27

    UART 2                       28

    UART 3                       29

   I2C2 30

   I2S                          31

    
We will not touch the real interfaces first, because when we touch the real interfaces, it may be difficult to understand without these concepts. It may be more helpful to understand the problem by browsing the relevant knowledge first and then studying it in more detail little by little.

In <asics and Practice>>, there are some matters regarding the use of VIC:

If the code is running in the on-chip RAM and the calling program needs to call an interrupt, the interrupt vector must be remapped to Flash address 0x0. This is done because all exception vectors are located at address 0x0 and above. This is achieved by configuring the register MEMMAP (located in the system control module) to RAM mode.

Although multiple interrupt sources can be selected to generate FIQ requests, there is only one dedicated interrupt service routine to service and respond to all FIQ requests. Therefore, if more than one interrupt is assigned as FIQ, the FIQ interrupt service routine must read the content of VICFIQStatus to decide how to handle the interrupt request. However, it is still recommended to assign only one interrupt as FIQ, as multiple FIQ interrupt sources will increase interrupt latency.

After the interrupt service routine is executed, clearing the peripheral interrupt flag will affect the corresponding bit in the VIC register (VICRawIntr, VICFIQStatus, VICIRQStatus). In addition, in order to service the next interrupt, the VICVectAddr register must be written before the interrupt returns. This write operation will clear the corresponding interrupt flag in the internal interrupt priority hardware.

Normally, to disable VIC interrupts, the corresponding bit in the VICIntEnClr register must be cleared. This operation clears the corresponding bit in the VICIntEnable register. This also applies to VICSoftInt, VICSoftIntClear. VICSoftIntClear will clear the corresponding bit in VICSoftInt. For example: VICSoftInt=0x0000 0005 and bit0 must be cleared, then use VICSoftIntClear=0x0000 0001 to achieve the operation. Before executing VICSoftIntClear=0x0000 0001, execute VICSoftIntClear=0x0000 0000 first. Remember.

The VICIntSelect register selects which one is IRQ and which one is FIQ according to the order in the figure above. When the corresponding bit is 1, the interrupt is FIQ, otherwise it is IRQ. VICIntEnable also determines which interrupt can be enabled in this order.

In the 21xx series, there are vector control registers VICVectCntl0~VICVectCntl15 representing 16 priorities, namely, VICVectCntl0 code slot0 priority (highest priority), VICVectCntl1 represents slot1 priority. In the VICVectCntl register, the lower five bits represent which interrupt, for example, if VICVectCntl0=0x0F, then from the sequence in the above figure, we know that ENT1, i.e. external interrupt 1, has the highest priority. The sixth bit in VICVectCntl represents whether IRQ is enabled, 1 represents enabled. In the 2400 series, VICVectPriority0~VICVe ctPriority31 is used to load the priority in the above figure. For example, if the number loaded by VICVectPriority31 is 0x12, which is 18 in decimal, according to the order of the above figure, the priority of AD0 is 31, which is the lowest priority. VICVectAddr0~VICVectAddr15 (31 in the 2400 series), each register corresponds to VICVectCntl (VICVectPriority). If this group of registers is not set, the VICDevVectAddr register is used in the 210x series. The corresponding register has not been found in the 2400 for the time being, but it doesn't matter. We may involve it when we study it later, so we will talk about it then.