Quickly learn Arm (33)--System Control Module (2)

We have discussed the reset issue before. In fact, the execution process of the four resets is not the same. After the external reset, the processor first determines the state of P2.10 to determine whether to allow the ISP code. The watchdog reset does not have this function. The following figure briefly describes the external reset process:

   The following figure shows the process of watchdog reset:

The four reset modes we have talked about have priorities. In order to distinguish the four reset sources, there is a flag in the RSID register that reflects the reset source.

The power-on reset has the highest priority and can clear other reset flags.

The watchdog reset has the lowest priority, and any other reset can clear its reset flag.

The brownout check reset and external reset have the same priority and cannot clear each other's interrupt flags.

Let's look at the hardware reset process again:

When the 1.8V power supply of the CPU reaches 1.65V, the on-chip RC oscillator starts to oscillate, and it takes some time to stabilize. In addition, during the power-on process, the reset signal needs to remain at a low level for a period of time until the oscillation signal stabilizes.

Once the internal oscillator is stable and the external reset signal is removed, the wake-up timer in the system starts counting the oscillator clock. After the count is full, the processor and all peripheral registers are restored to the default state. You can refer to the following figure for understanding: