LPC1768 clock

A phase-locked loop and CPU clock.

CPU clock = PLL 0 output / CPU clock configuration register pre-division value, that is: Fcpu = Fcco / CCLKCFG + 1. The phase-locked loop can multiply the external clock to a higher frequency. The PLL0 output frequency is:

Fcco = (2xMxFin)/N;

M=MSEL0+1, N=NSEL0+1. MSEL0 and NSEL0 are the low word and high word of PLL0CFG_Val respectively. The value range of N is 1~32, while the value of M is 6~512 at higher oscillator frequencies (over 1MHz).

After obtaining the PLL0 output value, the CPU clock can be obtained through the CPU clock configuration register.

In this system_lpc17xx.c file, just modify the macro definition value of #define PLL0CFG_Val 0x00050063.

For example: 00050063 In this state, PLL0 outputs 400MHz.

M = 0x63 (hexadecimal) + 1 = 100 (decimal);

N = 0x05 + 1 =  6;

Fcco = 2X12x100/6 = 400M

Fcpu=Fcco/2^（CCLKCFG+1）=400M/4=100M.

The frequency division value CCLKSEL can only be 0 and an odd value (1, 3, 5, ..., 255). CCLK is obtained from the output signal of PLL0 and is divided by CCLKSEL+1.

2. Timer clock: The timer can use PC and PR to re-divide

Pre-scaling factor: LPC_TIM1->PR

Timer count frequency = Fcclk/LPC_TIM1->PR

Reload value: LPC_TIM0->MR0

The time required for an interrupt = reload value/timer counting frequency.

http://blog.csdn.net/aquakguo0he1/article/details/8513923

void delayMs(uint8_t timer_num, uint32_t delayInMs)
{
  if ( timer_num == 0 )
  {
        LPC_TIM0->TCR = 0x02;                /* reset timer */
        LPC_TIM0->PR  = 0x00;                /* set prescaler to zero */
        LPC_TIM0->MR0 = delayInMs * (9000000 / 1000-1);
        LPC_TIM0->IR  = 0xff;                /* reset all interrrupts */
        LPC_TIM0->MCR = 0x04;                /* stop timer on match */
        LPC_TIM0->TCR = 0x01;                /* start timer */

        /* wait until delay time has elapsed */
        while (LPC_TIM0->TCR & 0x01);
  }
  else if ( timer_num == 1 )
  {
        LPC_TIM1->TCR = 0x02;                /* reset timer */
        LPC_TIM1->PR  = 0x00;                /* set prescaler to zero */
        LPC_TIM1->MR0 = delayInMs * (9000000 / 1000-1);
        LPC_TIM1->IR  = 0xff;                /* reset all interrrupts */
        LPC_TIM1->MCR = 0x04;                /* stop timer on match */
        LPC_TIM1->TCR = 0x01;                /* start timer */

        /* wait until delay time has elapsed */
        while (LPC_TIM1->TCR & 0x01);
  }
  return;
}

Two Systick:

2.1 Clock source: CPU provides P3.26 (STCLK)

2.2 10ms dedicated interrupt. If you want to generate interrupts cyclically, you must load STRELOAD regularly. The default time interval is in STCALIB

2.3 Bare metal dedicated timing timer