What is the difference between ARM7 and ARM-Cortex? Why does ARM have two startup modes?

Why does ARM have two boot modes? What is the difference between ARM7 and ARM-Cortex? What are fast interrupts and interrupts?

Why are there two boot modes for ARM (NAND FLASH and NOR FLASH)?

This is mainly determined by the different characteristics of the two FLASH.

NAND FLASH has a large capacity and the cost of storing unit bit data is much lower, but NAND FLASH must be read and written according to a specific timing, so the CPU cannot directly address the data in NAND FLASH. The CPU reads and writes data in NAND FLASH through a dedicated NAND flash controller, so NAND FLASH is more suitable for storing data.

NOR FLASH has a small capacity and fast speed. When reading and writing NOR FLASH, you input the address and then give the read and write signals to get data from the data bus. However, its price is higher than NAND FLASH, so it is suitable for program storage.

In summary, NOR FLASH can be directly connected to the arm bus, but DAND FLASH needs to be connected to S3S2440 through the NAND FLASH controller.

Difference between ARM7 and ARM-Cortex

ARM7: ARMv4 architecture, ARM9: ARMv5 architecture, ARM11: ARMv6 architecture, ARM-Cortex series: ARMv7 architecture.

ARM7 does not have MMU (memory management unit), it can only be called MCU (microcontroller), and cannot run modern multi-user multi-process operating systems such as Linux and WinCE, because running these systems requires MMU to allocate each user process its own independent address space. UCOS, UCLinux and other streamlined real-time RTOS do not need MMU, and of course they can run on ARM7.

ARM9 and ARM11 are embedded CPUs (processors) with MMU. They can run multi-user and multi-process operating systems such as Linux, and their application scenarios are also different from ARM7.

When it comes to the ARMv7 architecture, it starts to be named Cortex, and is divided into three series: Cortex-A, Cortex-R, and Cortex-M. The three series have clear division of labor: the "A" series is aimed at cutting-edge virtual memory-based operating systems and user applications; the "R" series is aimed at real-time systems; and the "M" series is for microcontrollers. Simply put, the Cortex-A series is a CPU for the mobile field, and the Cortex-R and Cortex-M series are MCUs for real-time control.

So ARM7 and Cortex-M look very similar, because they are both MCUs, but they are MCUs of different generations and architectures (Cortex-M is three generations higher than ARM7!), so there is a big difference in performance. In addition, the Cortex-M series is further divided into M0, M3, M4 and the ultra-low power M0+. Users choose chips based on factors such as cost, performance, and power consumption.

I believe you must know the difference between ARM7 and Cortex-M now, but I still spent some time to organize it here, which can help later beginners understand these basic conceptual issues.

ARM's FIQ (Fast Interrupt) IRQ (Interrupt)

IRQ, FIQ definition: This is a normal interrupt. When our program defines this interrupt, and an IRQ interrupt occurs when the program is running, the chip will run like this: the interrupt handler uses the IRQ request line to high-speed ARM, and ARM knows that an IRQ interrupt has come, and then ARM switches to IRQ mode. Similarly, if the interrupt is set to FIQ, then when the interrupt occurs, the interrupt handler tells ARM through the FIQ request line, and ARM knows that a FIQ interrupt has come, and then switches to FIQ mode.

So the question is, why do we have these two interrupts, or why are they divided into these two interrupts? The reason is simple, the speed is different, FIQ or fast interrupt is faster, so the question is again, why is FIQ faster???

reason:

1: ARM's FIQ mode provides more banked registers, r8 to r14 and SPSR, while IRQ mode does not have so many banked registers. There are no banked registers corresponding to R8, R9, R10, R11, and R12. This means that in ARM's IRQ mode, the interrupt handler must save the registers from R8 to R12 by itself, and then restore these registers when exiting the interrupt handler. In FIQ mode, since these registers are banked registers, the CPU automatically saves these values ​​to banked registers when the mode is switched, and automatically restores them when exiting FIQ mode. Therefore, this process of FIQ is faster than IRQ. Don't underestimate these registers. When ARM is compiled, if your FIQ interrupt handler is sufficient to use these independent registers to operate, it will not push general registers to the stack, which also saves some time.

2: FIQ has a higher priority than IRQ. If FIQ and IRQ are generated at the same time, FIQ is processed first.

3: In the Symbian system, when the CPU is in FIQ mode to handle FIQ interrupts, prefetch instruction exceptions, undefined instruction exceptions, software interrupts are all disabled, and all interrupts are masked. Therefore, FIQ will execute very quickly and will not be interrupted by other exceptions or interrupts, so it is faster than IRQ. However, IRQ is different. When ARM handles IRQ interrupts in IRQ mode, if a FIQ interrupt request comes, the IRQ interrupt handler being executed will be preempted, and ARM will switch to FIQ mode to execute this FIQ, so FIQ is much faster than IRQ.

4: In addition, the entry address of FIQ is 0x1c, and the entry address of IRQ is 0x18. Those who have written a complete assembly system understand the difference. 18 can only hold one instruction. In order not to conflict with the FIQ at 1C, this place can only jump. FIQ is different. There is no interrupt vector table after 1C. In this way, the interrupt handler of FIQ can be placed directly at 1C. Due to the limitation of the jump range, at least one jump instruction is missing.