ATtiny2313 General Registers

The register file is optimized for the AVR Enhanced RISC instruction set. To achieve the required performance and flexibility, the register file supports the following input/output schemes:
Output one 8-bit operand, input one 8-bit result
Output two 8-bit operands, input one 8-bit result
Output two 8-bit operands, input one 16-bit result
Output one 16-bit operand, input one 16-bit result

Figure 4 shows the structure of the CPU's 32 general working registers.

(Click on the image to enlarge)

Figure 4. AVR CPU General Working Registers

Most instructions that operate on the register file have direct access to all registers, and most such instructions execute in a single clock cycle.

As shown in Figure 4, each register has a data memory address, which maps them directly to the first 32 addresses of the user data space. Although the physical implementation of the register file is not SRAM, this memory organization has great flexibility in accessing registers because the X, Y, and Z registers can be set as pointers to any register.

In addition to being used as general-purpose registers, registers R26..R31 can also be used as address pointers for data indirect addressing. These three indirect addressing registers are shown in Figure 5.

Figure 5. X, Y, Z registers.
In different addressing modes, these address registers can implement fixed offset, automatic increment and decrement functions.
For details, please refer to the ATtiny2313 instruction set.

Note: In all the above pictures, the "$" in the address is changed to "0X".