Design of Digital Control Phase-Shift Signal Generator Based on AVR Microcontroller

1 Introduction

Phase shift signal generator is an important part of signal source, but traditional analog phase shift has many shortcomings, such as the phase shift output waveform is easily affected by the input waveform, the phase shift angle is related to the size and nature of the load, the phase shift accuracy is not high, the resolution is low, etc. Moreover, the traditional analog phase shift cannot achieve the phase shift of any waveform. This is mainly because the traditional analog phase shift is determined by the amplitude and phase characteristics of the phase shift circuit. The phase shift and amplitude attenuation of each harmonic of non-sinusoidal signals such as square waves, triangle waves, and sawtooth waves are inconsistent, which leads to the distortion of the output waveform. At present, the method of generating signal source using DDS technology has been widely used, but the dedicated DDS chip has very small internal digital signal jitter due to the use of specific integration technology, and cannot output high-quality analog signals. With the development of modern electronic technology, especially with the development of single-chip microcomputers and programmable technology, the digital phase shift technology has solved this problem well. Among the many single-chip microcomputers, AVR single-chip microcomputer is one of the latest single-chip microcomputer series, and its outstanding features are high speed and rich hardware resources on the chip. PLD products with FPGA as the core are the fastest-growing products in integrated circuits in recent years. FPGA chips can handle multiple tasks in parallel, with good high-speed performance (nanosecond execution speed) and high reliability of pure hardware systems. Using FPCA to implement DDS can solve many shortcomings of dedicated DDS chips. It can easily implement various complex frequency modulation, phase modulation and amplitude modulation functions as needed, and has good practicality.

This paper combines the AVR series MCU ATmega16 and FPGA Cyclone devices to implement a new design of a digital phase-shift signal generator for DDS. This solution is flexible and can be combined with other functional modules to expand into any signal generator.

2. System Overall Design and Implementation

It includes keyboard key control part, single-chip system part, FPGA part, amplitude control and D/A conversion circuit. The single-chip microcomputer uses ATmega16, which sends frequency control word and phase control word to FPGA according to the matrix keyboard input, which is used to set the frequency and phase of the output sine wave. The high-speed D/A converter is used for DA conversion of sine wave, and the reference voltage can be controlled by the amplitude control word of the single-chip microcomputer to achieve the purpose of digital amplitude modulation. FPGA constitutes the core part of DDS, which is used to receive the sent frequency word and phase word, and output sine wave data to the DA converter. The character LCD 1602A display screen is used to display the output frequency and phase in real time.

2.1 Communication between MCU and FPGA

The synchronous serial interface of ATmega16 allows high-speed synchronous data transmission between the chip and peripherals, or between several AVR microcontrollers, in a way compatible with the standard SPI interface protocol. In this system, ATmega16 is only responsible for sending data and does not need to receive data, so it is set to the host working mode.

2.2 Design of digital controlled phase shift signal generator

The main idea of ​​DDS is to synthesize the required waveform based on the concept of phase. It adopts a direct digital synthesis system with a phase accumulation oscillation method, and sets the phase accuracy of the sine wave to N bits, resulting in a resolution of 1/2N. The clock frequency fclk is used to read each point on the digital phase circle as the address, and the amplitude value of the sine wave in the corresponding ROM is matched, and then the sine wave is reconstructed through the DAC. The function of the phase accumulator is to read a value every M points when reading each point on the digital phase circle, so that the output sine wave frequency fsin is:

The digital phase-shift signal generator based on DDS is the core design part of the whole system, and its circuit model diagram is shown in Figure 4. This part is completely designed by VHDL language and implemented on FPGA Cyclone device. The circuit is required to output 2 sinusoidal signals, and the waveform output is realized by 2 10-bit D/A. The signal frequency can be synchronously controlled by the input 8-bit frequency control word; one of them is used as a reference signal, and the other is a phase-shiftable signal, which can be controlled by the input 8-bit phase control word. Among them, "FWORD" is an 8-bit frequency control word, which controls the frequency shift of the output waveform signal; "PWORD" is an 8-bit phase shift control word, which controls the phase shift of the output waveform; ADDER32B and AD-DER10B are 32-bit and 10-bit adders respectively; SIN_ROM is a ROM for storing waveform data, 10-bit data line, 10-bit address line (data and address lines can be up to 32 bits), and the sine wave data file is a file with the suffix mif, which can be directly generated by the C program. REG32B and REG10B are 32-bit and 10-bit registers respectively; POUT and FOUT are 8-bit outputs, which can be connected to two high-speed D/A to output reference signals and phase-shifted waveform signals respectively.

2.3 Design of Embedded Phase-Locked Loop

When the output waveform frequency is high, the waveform distortion will inevitably occur due to the decrease in the number of waveform data points sampled for a complete cycle. To eliminate waveform distortion, one method is to increase the number of points of the sampled waveform data, and the other is to increase the main working clock frequency of the system. If no external ROM is added, the latter method can be used. When designing this system, while making full use of the storage space of the FPGA, in order to increase the output frequency of the waveform (without distortion), the embedded phase-locked loop in the Cyclone device is also used to increase the main working clock frequency of the system. The main clock frequency in actual operation reaches 120 MHz.

3 Experimental conclusions

Through design and experiments, the following conclusions are drawn:

(1) This design controls the frequency and phase of the waveform output through the keyboard. The waveform frequency can be adjusted from 10 Hz to 15 MHz, the phase can be adjusted from 0° to 360°, and the minimum frequency step value is 1.795 15 Hz.

(2) The waveform distortion is related to the number of bits in the waveform ROM and the main operating clock frequency.

(3) Using the embedded phase-locked loop in the FPGA or increasing the number of points for sampling waveform data (external configuration ROM is required in this case) can greatly increase the frequency of the main working clock and eliminate waveform distortion. Which method to use or both methods depends on the needs of the actual application. The VHDL language has strong circuit description and modeling capabilities and can model and describe digital systems from multiple levels, thereby greatly simplifying the hardware design task and improving design efficiency and reliability.

(4) Based on the in-system reprogrammable features of FPGA and VHDL, system updates only require modifying the VHDL program without having to rebuild the system. The control of the peripheral circuit digital/analog converter can also be implemented by the VHDL program, so the digital/analog converter chip can be easily replaced.

(5) The use of ATmega16 microcontroller enables online programming, which is convenient and flexible, improving development efficiency. At the same time, the use of serial data transmission occupies fewer port lines and reduces resource waste.

(6) Compared with the dedicated DDS integrated chip, the DDS circuit in this design has better flexibility, can generate arbitrary waveforms, has high frequency resolution, fast conversion speed, good stability, high accuracy, and can realize program control of frequency, phase, and amplitude. More importantly, if it is used as an IP core, it will have greater portability.