ARM bare board development configuration process 1

ARM bare board is under development:

Can the C language program be run as soon as the development board is powered on?

Answer: No, ATPCS (arm and thumb program calling specifications) uses the resources in ARM by default, and the ARM resources have not been initialized when power is turned on!

[Solution:] Initialize the resources used by ATPCS in the boot phase of the bootloader. (bootloader = boot + loader)

By default, ATPCS uses the following resources in ARM:

1. R0-R3 (pass parameters to the function, only registers can be used in registers. When the input parameters exceed 4, they must be passed through the stack space), R0 (the return value of the function) ----> Initialization, not necessary (don't care)

2. Automatically protect r4-r12----> Push stack ----> stmfd sp!,{r4-r12} ----> SP must be initialized to point to a legal address

What to do in the boots phase:

1. Turn off watchdog and interrupt (enable cache)

2. Initialize the SOC clock controller

3. Initialize DRAM options, such as refresh cycles...

4. Initialize the value of SP in different modes. The characteristics of its value are high address, and this address must point to a readable and writable place (memory)

5. Result: Jump to main function normally

------------------------------------------------

Memory: RAM

Static SRAM works as long as there is voltage (network card)

Dynamic DRAM dynamic refresh works (memory module) 

-------------------------------------------------

Dealing with hardware:

unsigned int *p = addr; //Find address

p[x] = data; //assignment

ldr r1,=addr

ldr r0,=data

str r0,[r1]

----------------------------------------------------

On-chip resources === SFR ---》Locate the description of the specific controller and find REGISTER DESCRIPTION in the chip user manual

CPU: Registers r0-r15

Controller: Registers with addresses

Off-chip resources:

1. The watchdog is a controller. Turning it off means turning off the controller.

addr: address describing the resource of this controller 0xEA20_0000

x : range 0

data: See the chip manual for details. If it is just turned off, the binary set of 0x0 meets the requirements.

2. Initialize the clock

Clock === Frequency (overclocking) Generally, CPU manufacturers have reference values

clk : clock frequency

pll: phase-locked loop, frequency multiplication, frequency locking

y = f(a,b,c,fin);

y: output frequency fin: input frequency a,b,c: frequency multiplication factor

HCLK: High speed clock PCLK: Slow speed clock 

fin ----> pll -----> fout ----> DIV -----> armclk

12M |

|----DIV----> HCLK

|

|----DIV---> PCLK 

S5PC100: contains 3 buses, each bus manages which controllers

WDT: PCLK (slow clock) 

Commonly used registers:

APLL_MASK: Mask register lock time register

APLL_CON: Control register phase-locked loop coefficient configuration register

CLK_SRC: Clock selection register

CLK_DIV : Clock division register

3. Memory initialization

slightly

4. Initialize the value of SP

Point to memory, make sure not to point to the code area, and do not overwrite other segments.

Determine the first address of memory:

0x2000 0000

memory size:

256MB ------> 2^28 0x1000 0000

0x20008000 

usr svc irq

5. bl main

Lighting:

led 

unsigned int *p = addr;

p[x] = data;

1. First find the peripheral device and determine whether the device is an on-chip resource or an off-chip resource.

How to judge, it depends on whether the device has an address bus

2. General IO port

When there are only two states, 1 or 0, the corresponding registers are:

Configuration/Selection Registers Data Registers

The idea of ​​reuse: 

The first step is to configure the function, and then configure the controller according to the function.

GPIO:

【Set multiple bits】 

Read first, clear, set, write back