S3C2440 chip clock (1)

The clock and power management module consists of three parts: clock control, USB control and power control.

The clock control logic in S3C2440A can generate the necessary clock signals, including FCLK of CPU, HCLK of AHB bus peripherals and PCLK of APB bus peripherals. S3C2440A contains two phase-locked loops (PLL): one for FCLK, HCLK and PCLK, and the other for USB module (48MHz). The clock control logic can slow down the clock without using PLL, and the clock of each peripheral module can be connected or disconnected by software to reduce power consumption.

Regarding the power control logic, the S3C2440A includes various power management schemes to ensure optimal power consumption for a given task. The power management module in the S3C2440A can be activated into four modes: NORMAL mode, SLOW mode, IDLE mode, and SLEEP mode.

Normal mode: This mode provides clock to the CPU and all peripherals of the S3C2440A. In this mode, power consumption will reach the maximum when all peripherals are turned on. It allows the user to control the operation of peripherals by software. For example, if a timer is not necessary, the user can disconnect the clock connected to the timer (CLKCON register) to reduce power consumption.

SLOW mode: PLL-free mode. Unlike normal mode, SLOW mode uses an external clock (XTIpll or EXTCLK) directly as FCLK to S3C2440A without using PLL. In this mode, power consumption depends only on the frequency of the external clock. Power consumption due to PLL is excluded.

IDLE mode: This module only disconnects the CPU core clock (FCLK), but it provides clocks to all other peripherals. The idle mode results in reduced power consumption by the CPU core. Any interrupt request to the CPU can wake it up from the idle mode.

Sleep (SLEEP) mode: This module is separated from the internal power supply. Therefore, no power consumption occurs in this mode due to the CPU and internal logic except the wake-up logic. To activate the sleep mode, two independent power supplies are required. One of the two power supplies provides power to the wake-up logic. The other provides power to other internal logic including the CPU, and should be able to control the power on and off. In sleep mode, the second power supply for the CPU and internal logic will be turned off. Wake-up from sleep mode can be generated by EINT[15:0] or RTC alarm interrupt.

The block diagram of the clock structure shows that the main clock source comes from an external crystal (XTIpll) or an external clock (EXTCLK). The clock generation includes an oscillator (oscillator amplifier) ​​connected to the external crystal, and also contains two PLLs (phase-locked loops) required by the S3C2440A to generate high-frequency clocks.

Clock source selection