STM8S0 TIM1_PWM complementary output

Table of contents:

1. Timer 1 and complementary PWM basics

2. Procedure:

1. TIM1_CH1_PWM complementary + dead zone

2. TIM1_CH2_PWM complementary + dead zone

3. TIM1_CH1_PWM+TIM1_CH2_PWM complementary+dead zone

 3. To use IAR simulation, you need to set up: Select IAR menu ST-Link, select Option Bytes, and configure as shown in the figure (see the end of the article)

1. Timer 1 complementary PWM basics

1.TIM1 is an advanced timer, the timer is a 16-bit counter with 65536 frequency divisions, and the frequency division coefficient is 1-65536. The counting direction can be selected (divided into two counting directions: up and down).

2. Enable peripheral clock register (CLK_PCKENR): turn on or off the peripheral clock

3.TIM1_EGR: Event generation register, which can reinitialize the TIM1 timer

4. Control register 1 (TIM1_CR1): Address offset value: 0x00; Reset value: 0x00

5. Repeat count register (TIM1_RCR)

REP[7:0]: value of the repeat counter

When the preload function is enabled, these bits allow the user to set the update rate of the compare register (i.e., periodic transfer from the preload register to the current register); if update interrupts are enabled, the rate at which update interrupts are generated will also be affected.

Each time the down counter REP_CNT reaches 0, an update event is generated and the counter REP_CNT restarts from the REP value.

Since REP_CNT reloads the REP value only when the periodic update event U_RC occurs, the TIM1_RCR register

The new value written to the register takes effect only when the next periodic update event occurs.

This means that in PWM mode, (REP+1) corresponds to:

- Number of PWM cycles in edge-aligned mode;

- Number of PWM half cycles in centrosymmetric mode;

6. The pre-divider is divided into (TIM1_PSCRH) and (TIM1_PSCRL). When setting the pre-divider coefficient, the high bit (TIM1_PSCRH) must be in front and the low bit (TIM1_PSCRL) must be in the back.

The prescaler is used to divide the frequency of CK_PSC.

The counter clock frequency (fCK_CNT) is equal to fCK_PSC/(PSCR[15:0]+1).

PSCR contains the value that is currently loaded into the prescaler register when an update event occurs (an update event includes a counter being

TIM_EGR UG bit is cleared to 0 or is cleared to 0 by the slave controller operating in reset mode). This means that in order for the new value to take effect,

An update event shall be generated.

(Remember: the general timer can select 16 frequency divisions, and the basic timer can only select 8 frequency divisions)

7. Capture/Compare Enable Register 1 (TIM1_CCER1): For channels with complementary outputs, this bit needs to be preloaded.

8. Capture/compare register 1 is divided into high bit (TIM1_CCR1H) and low bit (TIM1_CCR1L) to configure the duty cycle value of PWM

If the CC1 channel is configured as output (CC1S bit in TIM1_CCMR1):

CCR1 contains the value that is currently loaded into the Capture/Compare 1 register (preload value).

If the preload function is not selected in the TIM1_CCMR1 register (OC1PE bit), the written value is immediately transferred to the current register.

Otherwise, this preload value is transferred to the current capture/compare 1 register only when an update event occurs.

The current capture/compare register value is compared with the value of the counter TIM1_CNT and generates an output signal on the OC1 port.

If the CC1 channel is configured as input:

CCR1 contains the counter value at the time of the last input capture 1 event (IC1) (this register is read-only at this time).

9. Automatically load register high (TIMx_ARRH) and automatically load register low (TIMx_ARRL) 

The reset values ​​of these two registers are 0x00. It should be noted that the advanced timer TIM1 and the general timers TIM2, TIM3, and TIM5 are all 16-bit counting timers. When operating the registers, the upper 8 bits must be written first and then the lower 8 bits. The basic timers TIM4 and TIM6 are 8-bit counting timers, which do not distinguish between the upper 8 bits and the lower 8 bits. Therefore, when operating the basic timers, the register name is (TIMx_ARR). When operating the reload register, the updated value will not be written into the reload register immediately, but the value of the operation will be written into the register when an interrupt is generated. Of course, software methods can also be used to generate interrupts.

10. Capture/Compare Mode Register 1 (TIM1_CCMR1):

The channel can be used for input (capture mode) or output (compare mode), and the direction of the channel is defined by the corresponding CC1S bit. The other bits of this register have different functions in input and output modes.

0C1M[2:0]: Output compare 1 mode

These 3 bits define the action of the output reference signal OC1REF, and OC1REF determines the value of OC1. OC1REF is high

Valid, and the valid level of OC1 depends on the CC1P bit.

000: Freeze. The comparison between the output compare register TIM1_CCR1 and the counter TIM1_CNT has no effect on OC1REF;

001: Set the output of channel 1 to a valid level when a match occurs. When the value of the counter TIM1_CNT matches the capture/compare register 1

(TIM1_CCR1) are the same, force OC1REF to be high.

010: Set the output of channel 1 to an invalid level when matching. When the value of counter TIM1_CNT matches the capture/compare register 1

(TIM1_CCR1) are the same, force OC1REF to be low.

011: Flip. When TIM1_CCR1 = TIM1_CNT, flip the level of OC1REF.

100: Forced to invalid level. Force OC1REF to low.

101: Forced to valid level. Force OC1REF to high.

110: PWM mode 1 - When counting up, once TIM1_CNT < TIM1_CCR1, channel 1 is at a valid level, otherwise

Invalid level; when counting down, once TIM1_CNT>TIM1_CCR1, channel 1 is invalid level (OC1REF=0),

Otherwise it is a valid level (OC1REF=1).

111: PWM mode 2 - When counting up, once TIM1_CNT < TIM1_CCR1, channel 1 is at an invalid level, otherwise

Is a valid level; when counting down, once TIM1_CNT>TIM1_CCR1, channel 1 is a valid level, otherwise it is invalid

Level

11. Control register 1 (TIMx_CR1) 

The reset value is 0x00, and this register applies to all timers. 

12. Brake register (TIM1_BKR)

2. Procedure:

1. TIM1_CH1_PWM complementary + dead zone

void PWM2_INIT()

{

    CLK_PCKENR2 |= 0x80; //Turn on the timer 1 peripheral clock

    TIM1_EGR |= 0x01; //Reinitialize TIM1 

    TIM1_CR1 = 0x00; //B7(0) can be written directly to B65(00) edge alignment mode B4(0) counts up B3(0) counter does not stop update event occurs

    TIM1_RCR = 0x00;  

    TIM1_PSCRH =0; //Set pre-scaling to 16 divisions 16M

    TIM1_PSCRL =0x00; //PWM clock affects the cycle

    TIM1_CCER1 = 0x0F; //CC2ER1 is turned on 1, 2, high level is valid

    TIM1_CCMR1 = 0x60; //PWM mode 1, CC1 configuration input and output

    TIM1_ARRH = 0x03; //Set reload value

    TIM1_ARRL = 0xe7; //PWM period 

    TIM1_CCR1H = 0x01;

    TIM1_CCR1L = 0xf4; //Duty cycle value

    TIM1_CR1 |= 0x01; // Enable TIM1 counter

    TIM1_DTR = 0x50; // Deadtime generator

    TIM1_BKR |= 0x80;

}

2. TIM1_CH2_PWM complementary + dead zone

void PWM2_INIT()

{

    CLK_PCKENR1 |= 0x80; //Turn on the timer 1 peripheral clock

    TIM1_EGR |= 0x01; //Reinitialize TIM1 

    TIM1_CR1 = 0x00; //B7(0) can be written directly to B65(00) edge alignment mode B4(0) counts up B3(0) counter does not stop update event occurs

    TIM1_RCR = 0x00;  

    TIM1_PSCRH =0; //Set pre-scaling to 16 divisions 16M

    TIM1_PSCRL =0x00; //PWM clock affects the cycle

    TIM1_CCER1 = 0xf0; //CC2ER1 is turned on 1,2, high level is valid

    TIM1_CCMR2 = 0x60; //PWM mode 1, CC1 configuration input and output

    TIM1_ARRH = 0x03; //Set reload value

    TIM1_ARRL = 0xe7; //PWM period 

    TIM1_CCR2H = 0x01;

    TIM1_CCR2L = 0xf4; //Duty cycle value

    TIM1_CR1 |= 0x01; // Enable TIM1 counter

TIM1_DTR = 0x50; // Deadtime generator

    TIM1_BKR |= 0x80;

}

3. TIM1_CH1_PWM+TIM1_CH2_PWM complementary+dead zone

void PWM2_INIT()

{

    CLK_PCKENR1 |= 0x80; //Turn on the timer 1 peripheral clock

    TIM1_EGR |= 0x01; //Reinitialize TIM1 

    TIM1_CR1 = 0x00; //B7(0) can be written directly to B65(00) edge alignment mode B4(0) counts up B3(0) counter does not stop update event occurs

    TIM1_RCR = 0x00;  

    TIM1_PSCRH =0; //Set pre-scaling to 16 divisions 16M

    TIM1_PSCRL =0x00; //PWM clock affects the cycle

    TIM1_CCER1 = 0xff; //CC2ER1 is turned on 1,2, high level is valid

    TIM1_CCMR1 = 0x60; //PWM mode 1, CC1 configuration input and output

    TIM1_CCMR2 = 0x60; //PWM mode 1, CC1 configuration input and output

    TIM1_ARRH = 0x03; //Set reload value

    TIM1_ARRL = 0xe7; //PWM period 

    TIM1_CCR1H = 0x01;

    TIM1_CCR1L = 0xf4; //Duty cycle value

    TIM1_CCR2H = 0x01;

    TIM1_CCR2L = 0xf4; //Duty cycle value

    TIM1_CR1 |= 0x01; // Enable TIM1 counter

TIM1_DTR = 0x50; // Deadtime generator

    TIM1_BKR |= 0x80;

}

3. To use IAR simulation, you need to set up: Select IAR menu ST-Link, select Option Bytes, and configure as shown in the figure

The procedure is as follows: It can be used after personal testing.

#include

/*

//TIM1_CH1_PWM complementary + dead zone

void PWM2_INIT()

{

    CLK_PCKENR2 |= 0x80; //Turn on the timer 1 peripheral clock

    TIM1_EGR |= 0x01; //Reinitialize TIM1 

    TIM1_CR1 = 0x00; //B7(0) can be written directly to B65(00) edge alignment mode B4(0) counts up B3(0) counter does not stop update event occurs

    TIM1_RCR = 0x00;  

    TIM1_PSCRH =0; //Set pre-scaling to 16 divisions 16M

    TIM1_PSCRL =0x00; //PWM clock affects the cycle

    TIM1_CCER1 = 0x0F; //CC2ER1 is turned on 1, 2, high level is valid

    TIM1_CCMR1 = 0x60; //PWM mode 1, CC1 configuration input and output

    TIM1_ARRH = 0x03; //Set reload value

    TIM1_ARRL = 0xe7; //PWM period 

    TIM1_CCR1H = 0x01;

    TIM1_CCR1L = 0xf4; //Duty cycle value

    TIM1_CR1 |= 0x01; // Enable TIM1 counter

    TIM1_DTR = 0x50; // Deadtime generator

    TIM1_BKR |= 0x80;

}

*/

/*

//TIM1_CH2_PWM complementary + dead zone

void PWM2_INIT()

{

    CLK_PCKENR1 |= 0x80; //Turn on the timer 1 peripheral clock

    TIM1_EGR |= 0x01; //Reinitialize TIM1 

    TIM1_CR1 = 0x00; //B7(0) can be written directly to B65(00) edge alignment mode B4(0) counts up B3(0) counter does not stop update event occurs