ARM S3C2410 Learning Notes

1. Introduction to S3C2410 processor

2410 is a 16/32-bit RISC embedded system microprocessor based on the ARM920T core from Samsung, mainly for handheld devices and low-power, cost-effective applications. The frequency reaches 203Mhz. The ARM920T core consists of three parts: the ARM9TDMI core, the memory management unit (MMU) and the cache. The cache consists of independent 16KB address and 16KB data caches. The ARM920T has two coprocessors, CP14 and CP15. CP14 is used for debug control and CP15 is used for storage system control and test control.

Resources include:

◆1 LCD controller (supports STN and TFT screens).

◆1 SDRAM controller, 1 NAND Flash controller.

◆3 channels of UART.

◆4 channels of DMA.

◆4 timers with PWM function and an internal clock.

◆8-channel 10-bit ADC

◆Touch screen interface.

◆IIS bus, IIC bus.

◆2 USB host interfaces and 1 USB device interface.

◆2 SPI interfaces, SD interface and MMC card interface.

◆Watchdog counter.

◆117 general purpose I/Os and 24 external interrupt sources.

2. Storage space settings of S3C2410

S3C2410 divides the system's storage space into 8 groups (Banks), each with a size of 128MB, for a total of 1GB. The starting addresses of Bank0 to Bank5 are fixed, while the starting address of Bank7 is the ending address of Bank6 and is adjustable. Bank6 and 7 are used for ROM, SRAM or SDRAM. The access cycle, clock delay and other parameters of all memory blocks can be set separately.

S3C2410 has three startup modes, which can be selected through the OM[1:0] pins:

◆When OM[1:0]=00, the processor boots from NAND Flash.

◆OM[1:0]=01 means the processor boots from a 16-bit wide ROM.

◆OM[1:0]=10 means the processor boots from a 32-bit wide ROM.

If the system is set to boot from NAND Flash, the processor will automatically load the first 4KB code content in NAND Flash into the on-chip steppingstone SRAM during startup, and then the system reads the code from SRAM for execution. After that, the boot program in SRAM should complete the work of loading the code from FLASH to SDRAM. After the startup is completed, the 4KB SRAM can be used for other purposes. If it is started in another way, the ROM must be located at 0x00000000, and the 4KB startup SRAM is placed at 0x40000000. The memory mapped to the space of nGCS0 chip select is the startup memory.