ARM instruction set version and ARM version

The first processor to feature Thumb technology was the ARM7TDMI. All ARM9 and later families, including XScale, have incorporated Thumb technology.

Jazelle

ARM has also developed a technology, Jazelle DBX (Direct Bytecode eXecution), that allows them to accelerate the running of Java bytecode on certain hardware architectures, just like other operating modes, when calling some special software that cannot support bytecodes, it can provide accelerated running of certain bytecodes. It can run between existing ARM and Thumb modes.

The first processor to feature Jazelle technology is the "ARM7EJ-S": Jazelle is indicated by a 'J' in the CPU name. It is used to allow mobile phone manufacturers to accelerate Java ME games and applications, thus prompting the continued development of this technology.

Thumb-2

Thumb-2 technology was first seen in the "ARM1156 core" and was released in 2003. Thumb-2 expands the limited 16-bit Thumb instruction set to allow for a wider range of instruction sets with additional 32-bit instructions. Therefore, the expected goal of Thumb-2 is to achieve a coding density close to that of Thumb, but with performance close to that of the ARM instruction set with 32-bit memory.

Thumb-2 has also derived a variety of instructions from the ARM and Thumb instruction sets, including bit column operations, branch table building, and conditional execution.

Thumb Execution Environment (ThumbEE)

ThumbEE, also known as Thumb-2EE, is known as Jazelle RCT technology in the industry. It was released in 2005 and first appeared in the "Cortex-A8" processor. ThumbEE provides some extensions from Thumb-2, making the instruction set particularly suitable for runtime code generation (such as real-time compilation) in the operating environment. Thumb-2EE is designed for some languages ​​such as Limbo, Java, C#, Perl and Python, and allows the real-time compiler to output smaller compiled code without affecting performance.

New features provided by ThumbEE include automatic checking for invalid pointers every time an instruction is accessed, an instruction that can perform array range checks, and the ability to branch to the classifier, which contains a small set of frequently called code, typically used to implement high-level language features, such as allocating memory for a new object.

Advanced SIMD (NEON)

Advanced SIMD extensions, known as "NEON" technology in the industry, is a combination of 64-bit and 128-bit single instruction multiple instruction sets (SIMD), which has standardized acceleration capabilities for multimedia and signal processing programs. NEON can run MP3 audio decoding on a 10 MHz processor and can run adaptive multi-rate audio compression encoding below 13 MHz. NEON has a wide range of instruction sets, their own register arrays, and independently running hardware. NEON supports 8, 16, 32 and 64-bit integers and single-precision floating-point data, and operates in a single instruction multiplexed manner to run the voice and video parts of graphics and game processing. The single instruction multiple instruction set is a decisive factor in vector superprocessors, which have multiple processing capabilities at the same time. In NEON technology, SIMD can perform up to 16 operations at the same time.

VFP

VFP (Vector Floating Point) is a derivative technology for the ARM architecture in the coprocessor. It provides low-cost single-precision and double-precision floating-point computing capabilities and is fully compatible with the ANSI/IEEE Std 754-1985 binary floating-point arithmetic standard. VFP provides most applications suitable for floating-point operations, such as PDAs, smart phones, voice compression and decompression, 3D graphics and digital sound effects, printers, set-top boxes, and automotive applications. The VFP architecture also supports SIMD parallelization of short vector instructions. This is very helpful in reducing code size and increasing output efficiency in applications such as image and signal processing.

In ARM-based processors, other visible floating-point or SIMD coprocessors include FPA, FPE, and iwMMXt. They provide VFP-like functionality, but are not compatible at the opcode level.