ARM assembly: What do IA, IB, DA, DB and FD, ED, FA, EA mean in assembly?

In the multiple data transfer (STM, LDM) of ARM instructions, it is mentioned that the Load and Store instructions of multiple registers are divided into 2 groups:

A set of data storage and reading, corresponding to IA, IB, DA, DB,

One set is used for stack operations, corresponding to FD, ED, FA, EA,

The corresponding instructions in the two groups have the same meaning.

IA: increase after; indicates that the address increases after data transmission

IB: increase before

DA: decrease after

DB: decrease before

Right now:

STMIB (address increments first and then completes the operation)

STMFA (Full Incrementing Stack)

STMIA (Complete Operation Then Increment Address)

STMEA (empty incrementing stack)

STMDB (address is reduced first and then the operation is completed)

STMFD (full decrementing stack)

STMDA (complete operation and then decrement address)

STMED (empty decrementing stack)

The two commands in the above groups have the same meaning but are applicable to different occasions. Similarly, there are:

LDMIB, LDMED;

LDMIA, LDMFD;

LDMDB, LDMEA;

LDMDA, LDMFA.

IA mode means: after each transmission, the address is increased by 4; (After Increase)

DB mode means: before each transmission, the address is -4; (Before Decrease)

There are 8 modes for multi-register load/store instructions (4 for data block transfers and 4 for stack operations)

The STMDB and LDMIA instructions are generally used in pairs. STMDB is used to push registers onto the stack, and LDMIA is used to pop registers off the stack. Their function is to save the used registers.

Example 1:

Instruction: stmdb sp!,{r0-r12,lr}

Meaning: sp = sp - 4, first press lr, sp = lr (that is, put the content in lr into the memory address pointed to by sp). sp = sp - 4, then press r12, sp = r12. sp = sp - 4, then press r11, sp = r11...sp = sp - 4, finally press r0, sp = r0.

If you want to pop out r0-r12 and lr, you can use the ldmia instruction: ldmia sp!,{r0-r12,lr}

Example 2:

STMIA, for example, if the current memory address pointed to by r0 is 0x1000, STMIA R0!,{R1-R7} means first storing r1 at 0x1000, then r2 at 0x1004, then r3 at 0x1008. If it is a 32-bit processor, 4 bytes are added each time, and r1-r7 are stored in increasing addresses. This r0! means starting from the address of r0. STMDB means that the address decreases from r0 and is stored in sequence.

Example 3:

LDMIA:LDM means multiple register access. The following parameters are separated by “,”. The first parameter is the first address; the second parameter is the register list, which is enclosed in “{}”.

LDMIA R0!, {R1-R4}; R0 represents the first address of the storage space to be operated. The number of data to be operated is determined by the register list, which is now R1 to R4, a total of 4 data (each data is 32 bits)

specific:

The data in the storage space at address R0 is assigned to R1

The data in the storage space at address R0+4 is assigned to R2

The data in the storage space at address R0+8 is assigned to R3

The data in the storage space at address R0+12 is assigned to R4

The storage space and register status of all example instructions before execution:

mem32[0x1000C] = 0x04

mem32[0x10008] = 0x03

mem32[0x10004] = 0x02

mem32[0x10000] = 0x01

r0 = 0x00010000

r1 = 0x00000000

r3 = 0x00000000

r4 = 0x00000000

After execution, the storage space remains unchanged, but the registers change:

r0 = 0x00010010

r1 = 0x01

r2 = 0x02

r3 = 0x03

r4 = 0x04