STM32 DMA principle

1. Introduction to DMA

1. Introduction to DMA

　　DMA (Direct Memory Access) is a data transfer method that can greatly reduce the CPU workload.

　　The CPU has many functions such as transferring data, computing, and controlling program transfer, but in fact, data transfer (especially large amounts of data transfer) does not require the CPU to participate. For example, if you want to copy the data of peripheral A to peripheral B, you only need to provide a data path for the two peripherals and add some components to control the transfer to complete the data copy.

　　DMA is designed based on the above assumptions. Its function is to solve the problem of excessive consumption of CPU resources by large-scale data transfer. With DMA, the CPU can focus more on more practical operations - calculation, control, etc.

2. Working principle of DMA　

　　The role of DMA is to realize direct data transmission, and remove the link that traditional data transmission requires the participation of CPU registers. It mainly involves four types of data transmission, but they are essentially the same, all of which are transferred from one area of ​​memory to another area of ​​memory (the data register of the peripheral is essentially a storage unit of the memory). The four types of data transmission are as follows:

Peripherals to memory

Memory to peripherals

Memory to Memory

Peripheral to Peripheral

　　When the user sets the parameters, mainly involving the source address, target address, and transfer data volume, the DMA controller will start data transfer, and the end point of the transfer is when the remaining transfer data volume is 0 (this is not the case for cyclic transfer). In other words, as long as the remaining transfer data volume is not 0 and the DMA is in the enabled state, data transfer will occur.　　

3. Does DMA affect the operation of the CPU?

　　In an X86 architecture system, when DMA is in operation (assuming we copy a file from a disk to a USB drive), DMA actually occupies a portion of the system bus cycle. That is, before DMA is enabled, the system bus may be completely used by the CPU; when DMA is enabled, the system bus must allocate a certain amount of time for DMA to ensure that DMA and the CPU operate simultaneously. Obviously, DMA will reduce the CPU's operating speed.

　　In the STM32 controller, the chip adopts the Cortex-M3 architecture, and the bus structure has been greatly optimized. DMA occupies another bus and does not conflict with the CPU system bus. In other words, the use of DMA will not affect the operating speed of the CPU.

2. DMA structure of STM32

1. Main characteristics of DMA

● 12 independent configurable channels (requests) DMA1 has 7 channels, DMA2 has 5 channels 

● Each channel is directly connected to a dedicated hardware DMA request, and each channel also supports software triggering. These functions are configured through software. 

● The priority among the seven requests can be set by software programming (there are four levels: very high, high, medium and low), if equal priority is determined by hardware (request 0 takes precedence over request 1, and so on). 

● Independent transfer widths (byte, halfword, fullword) of the source and destination data areas, simulating the packing and unpacking process. The source and destination addresses must be aligned according to the data transfer width. 

● Supports circular buffer management 

● Each channel has three event flags (DMA half transfer, DMA transfer complete and DMA transfer error). These three event flags are logically ORed into a single interrupt request. 

● Transfer between storage devices 

● Transmission between peripherals and memory, memory and peripherals 

● Flash memory, SRAM, peripheral SRAM, APB1 APB2 and AHB peripherals can all be used as sources and destinations for access. 

● Programmable data transmission number: Maximum 65536

The following is a functional block diagram:

2. Two DMA controller structures

① DMA1 controller

② DMA2 controller

3. DMA register list

① Interrupt class

DMA_ISR: DMA Interrupt Status Register

DMA_IFCR: DMA interrupt flag clear register

Description: DMA1 and DMA2 each have a set of registers.

② Control transmission

DMA_CCRx: DMA channel x configuration register　

DMA_CNDTRx: DMA channel x data quantity register

DMA_CPARx: DMA channel x peripheral address register

DMA_CMARx: DMA channel x memory address register

illustrate:    

1> Each channel has a set of registers.

2> There is no difference between DMA_CPARx and DMA_CMARx, they can both store the addresses of peripherals and memory. DMA_CPARx and DMA_CMARx are just named differently.

4. DMA working characteristics of STM32

① Necessary conditions for DMA data transmission

The remaining transmission data volume is greater than 0

DMA channel transfer enable

There is an event request for DMA data transfer on the channel

　 The first two are easy to understand, but the third point does require detailed explanation. Please see the following three points.

② Transmission from peripheral to XX direction

　　Assuming that the data is transferred from ADC to memory, the source address of ADC's DMA transfer is obviously the ADC's data register. This does not mean that data transfer will be performed immediately once the DMA channel transfer is enabled. Only when an ADC conversion is completed and the transfer event of the ADC's DMA channel is valid, will DMA read data from the ADC's data register and write it to the destination address. When DMA reads the ADC's data register, it also invalidates the ADC's DMA channel transfer event. Obviously, data transfer can only be started again after the next ADC conversion is completed.

③DMA transfer from memory to XX

　 Because the data is ready, unlike ADC, it does not need to wait for the data to arrive. Therefore, there is no need for events corresponding to the channel. As long as DMA data transmission is enabled, it will continue to transmit until the set transmission amount is reached.

example:

1. Memory to memory

　　DMA transfer request is always valid

2. Memory to serial port 

　　DMA transfer request is always valid

One explanation:

　　The setting of memory to memory is equivalent to the validity of the event of the corresponding channel. The validity of the event of the corresponding channel and the setting of memory to memory are the trigger bits of the transfer. Each time the event of a transfer is set once, a transfer is completed. If the DMA transfer is triggered by the peripheral, the corresponding transfer event will be set to invalid after the transfer is completed. For memory to memory transfer, after a transfer is completed, the corresponding event will remain valid until the set transfer amount is completed.  

④When the peripheral works in DMA mode, can it be operated in software mode?

　 One thing is certain, when the peripheral is transmitting data in DMA mode, it is impossible to respond to the software control command of the CPU, otherwise it is illogical.

　 However, if the peripheral is only configured to work in DMA mode, but no DMA request is generated, data transmission is not performed. At this time, the software control command can still control the peripheral. This is the test conclusion obtained by the author when the serial port sends data in DMA mode.