Detailed explanation of GPIO in STM32 learning

GPIO:

STM32 has 3 (64-pin) IO ports, namely PA, PB, and PC.

The IO ports of STM32 can be configured into 8 modes by software:

1. Input floating

2. Input pull-up

3. Input drop-down

4. Analog Input

5. Open drain output

6. Push-pull output

7. Push-pull multiplexing function

8. Open-drain multiplexing function

Each IO port of STM32 is controlled by 7 registers. They are: 2 32-bit port configuration registers CRL and CRH in configuration mode; 2 32-bit data registers IDR and ODR; 1 32-bit set/reset register BSRR; 1 16-bit reset register BRR; 1 32-bit latch register LCKR; There are only 4 IO port registers we commonly use: CRL, CRH, IDR, ODR.

Note (When configuring STM32 peripherals, always enable the clock of the peripheral first! APB2ENR is the peripheral clock enable register on the APB2 bus)

1.CRL and CRH registers-->control whether the IO port is output or input.

The CRL of STM32 controls the mode of the lower 8 bits of each IO port (A~G) (for example, PA0-PA7). Each IO port occupies 4 bits of CRL, the upper two bits are CNF, and the lower two bits are MODE. Here we can remember several commonly used configurations, such as 0X4 for analog input mode (for ADC), 0X3 for push-pull output mode (for output port, 50M rate), 0X8 for pull-up/pull-down input mode (for input port), and 0XB for multiplexed output (using the second function of the IO port, 50M rate).

The CRH of STM32 controls the mode of the upper 8 bits of each IO port (A~G) (for example, PA8-PA15). Each IO port occupies 4 bits of CRH, the upper two bits are CNF, and the lower two bits are MODE.

2. IDR register and ODR register--"Read the content of the pin input (high or low) and control the content of your output (high or low)

IDR is a port input data register, which uses only the lower 16 bits. This register is a read-only register and can only be read in 16-bit form. The read value is the status of the corresponding IO port.

ODR is a port output data register, and only the lower 16 bits are used. Although this register is readable and writable, the data read from this register are all 0. Only writing is valid. Its function is to control the output of the port.

3. BSRR port bit set/clear register and BRR port reset register

I have used the BSRR register for a while, and I don't know how to use other registers. I just feel that it is very easy to use. It is very convenient to use. For example, if you have configured the port and want PA5 to output "1", then GPIOA->BSRR |= (1<<5); 5 is the corresponding register. It outputs "0", the same.

GPIO->BSRR |=(1<<(5+16)); You know why 16 is added.

The BRR and BSRR operations are the same.

When using ODR to operate the PC port, because the main program and interrupts operate the IO port at the same time (the main program sets PC3, and the interrupt sets PC6), using ODR to set it may cause unexpected situations. Online debugging shows that the values ​​of the GPIO registers are both correct, but the actual output is incorrect. If ODR is not used, and BRR and BSRR are used to implement the IO port settings, this problem will not occur and everything will be correct.

When referring to the manual describing BRR and BSRR, I found a few sentences (in the GPIO chapter):

"Each I/O port bit is freely programmable, however the I/O port registers must be accessed as 32-bit words (halfword or byte accesses are not allowed). The GPIOx_BSRR and GPIOx_BRR registers allow independent access to read/change any GPIO register; this way, there is no hazard if an IRQ is generated between read and change accesses."

"When programming individual bits of GPIOx_ODR, software does not need to disable interrupts: in a single APB2 write operation, only one or more bits can be changed. This is done by writing a '1' to the bits you want to change in the 'Set/Reset Register' (GPIOx_BSRR, for reset it is GPIOx_BRR). The bits not selected will not be changed."

The final conclusion is that if you need to set the IO port in the interrupt, it is best to use BSRR and BRR operations instead of ODR.