The relationship between PC and LR in ARM

What is the relationship between PC and LR that we often hear about? I finally figured it out this time. We all know that LR points to the address that PC will execute next time, but they have different relationships in different working modes of ARM. ARM has the following working modes: user mode, FIQ mode, IRQ mode, system mode, termination mode, data access termination mode, and undefined mode. ARM is a three-stage pipeline: instruction fetch, decode, and execute. ARM's R15 (PC) always points to the place where the instruction is fetched, and we always use execution as the reference point for analysis. Note that the place where the instruction is fetched is at a high address. When ARM is in ARM instructions, the length of each instruction is 4, PC = current execution + 8. Of course, if it is in THUMB instructions, the length of each instruction is 2, PC = current execution + 4.

   When a function call occurs in the program, the address returned by the function is stored in LR. When an interrupt occurs, the different modes are as follows:

(1) SWI and undefined interrupts

At this time, the address of the PC pointer has not been updated, so the content of LR is PC-4.

Instruction address:

A PC-8

A+4 PC-4 ;LR

A+8 PC ;PC

    When an interrupt occurs, it can directly return to the next instruction (PC-4) of A (PC-8), so when executing, just change LR to PC. To put it simply, when these two exceptions occur, the PC pointer is not updated and is still equal to A+8, which is the original value. When returning, it can be executed directly at LR.

      Return instruction: MOV PC,LR

(2) FIQ and IRQ interrupts

    In these two types of interrupts, the interrupt always starts after executing an instruction, but at this time the PC is updated, that is, the PC value must not be A+8, but A+12, then the corresponding LR also becomes A+8 (PC-4).

If it returns, it will start executing at LR(A+8), thus skipping the address A+4 and executing one less instruction. So when these two interrupts occur, it should return to LR -4.

         Before interruption:

APC-8

A+4 PC -4 ;LR

A+8 PC;PC

After the interruption:

A PC-12 Interrupted here

A+4 PC-8 ; skipped and not executed

A+8 PC-4; LR

A+12 PC ; Updated

    To put it more clearly, for example, when the CPU is interrupted while executing instruction D, the interrupt will not be processed before the instruction D is completed. After the execution, the PC has been updated, and the value of PC-4 is given to LR. This is determined by the system and cannot be modified by the software. That is, A+8. When the interrupt returns, the next instruction that has not been executed should be executed, that is, A+4, so when returning, LR-4 is set, so when returning, PC=LR-4. The return instruction is: SUB PC,LR,#4

(3) Instruction abort mode interrupt

    When an interrupt in this mode occurs, the PC will not be updated, but it will be re-executed at the location where the interrupt occurred. Because the CPU was interrupted while executing an instruction, the instruction may not have been completed or has not been executed yet, so the instruction must be re-executed.

Command mode:

A PC-8; Instruction abort interrupt occurs here

A+4 PC-4 ;LR

A+8 PC ;

   Therefore, when an interrupt occurs, the PC is not updated, that is, PC = A+8. At this time, LR = PC-4, that is, A+4. Because it is necessary to re-execute from the interrupted instruction, that is, re-execute from A, it returns to LR-4. Return instruction: SUB PC, LR, #4

(4) Data access abort mode interrupt

   This interrupt mode is aborted when accessing data, so it is necessary to re-execute from here just like the instruction abort, but the difference is that the PC has been updated at this time, not A+8, but A+12. Similar to the above situation, the value of LR is PC-4, that is, A+8, so to return to the interrupted instruction, it is necessary to return to LR-8. The return instruction is:

SUB PC, LR, #8.

   Summary: In short, only data access abort, FIQ and IRQ can cause PC to update. Others will not cause PC to update. However, in different working modes, the address of interrupt return execution is different. This should be noted.